Attention is currently required from: Ravi kumar, Furquan Shaikh, Arthur Heymans, Prasad Malisetty. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57615 )
Change subject: libpayload: Add support for PCI MMIO CONFIG access. ......................................................................
Patch Set 18:
(1 comment)
File payloads/libpayload/drivers/pci_ops.c:
https://review.coreboot.org/c/coreboot/+/57615/comment/75948de3_c7ace065 PS17, Line 34: uintptr_t get_pci_mmio_cfgbase(pcidev_t dev)
ATU configuration needed for every config/mem read/write. […]
Hi Prasad. Sorry if I was unclear. I meant that the code should be functionally equivalent to the code implemented in coreboot, specifically the pcicfg() function that I proposed which does the address translation that needs to be run for every read/write: https://review.coreboot.org/c/coreboot/+/58668/4/src/soc/qualcomm/sc7280/pci...
My assumption is that in the future, you will need to map > 1 device at a time in the MMIO space. Is that not true?
Also, please take a look at CB:57861 for the details on how we are reorganizing everything.
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Shelley Chen (Code Review)