Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/gpio: do some fixes in code style ......................................................................
soc/intel/gpio: do some fixes in code style
Change-Id: Ib4b4c28153398b6275728b28bda90e527d97e823 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 96 insertions(+), 94 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41035/1
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 713c808..f0d899d 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -146,7 +146,7 @@ #define PAD_CFG0_BUF_NO_DISABLE (0) #define PAD_CFG0_BUF_TX_DISABLE PAD_CFG0_TX_DISABLE #define PAD_CFG0_BUF_RX_DISABLE PAD_CFG0_RX_DISABLE -#define PAD_CFG0_BUF_TX_RX_DISABLE \ +#define PAD_CFG0_BUF_TX_RX_DISABLE \ (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE)
#define PAD_BUF(value) PAD_CFG0_BUF_##value @@ -159,17 +159,17 @@ #define PAD_IOSTERM(value) 0 #endif
-#define PAD_IRQ_CFG(route, trig, inv) \ - (PAD_IRQ_ROUTE(route) | \ - PAD_TRIG(trig) | \ - PAD_RX_POL(inv)) +#define PAD_IRQ_CFG(route, trig, inv) \ + (PAD_IRQ_ROUTE(route) | \ + PAD_TRIG(trig) | \ + PAD_RX_POL(inv))
#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) -#define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ - (PAD_IRQ_ROUTE(route1) | \ - PAD_IRQ_ROUTE(route2) | \ - PAD_TRIG(trig) | \ - PAD_RX_POL(inv)) +#define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ + (PAD_IRQ_ROUTE(route1) | \ + PAD_IRQ_ROUTE(route2) | \ + PAD_TRIG(trig) | \ + PAD_RX_POL(inv)) #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */
#define _PAD_CFG_STRUCT(__pad, __config0, __config1) \ @@ -202,9 +202,10 @@ * Set native function with RX Level/Edge configuration and disable * input/output buffer if necessary */ -#define PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_TRIG(trig) | \ - PAD_BUF(bufdis) | PAD_FUNC(func), \ +#define PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(bufdis) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) @@ -244,56 +245,57 @@ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
/* General purpose output, no pullup/down. */ -#define PAD_CFG_GPO(pad, val, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ +#define PAD_CFG_GPO(pad, val, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE))
/* General purpose output, with termination specified */ -#define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ +#define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
/* General purpose output, no pullup/down. */ -#define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ - PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG_OWN_GPIO(DRIVER)) +#define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | \ + PAD_CFG_OWN_GPIO(DRIVER))
/* General purpose output. */ #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm))
/* General purpose input */ -#define PAD_CFG_GPI(pad, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ +#define PAD_CFG_GPI(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
-#define PAD_CFG_GPI_IOSSTATE(pad, pull, rst, iosstate) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ +#define PAD_CFG_GPI_IOSSTATE(pad, pull, rst, iosstate) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate))
-#define PAD_CFG_GPI_IOSSTATE_IOSTERM(pad, pull, rst, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ +#define PAD_CFG_GPI_IOSSTATE_IOSTERM(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
/* * General purpose input. The following macro sets the * Host Software Pad Ownership to GPIO Driver mode. */ -#define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ +#define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE) | PAD_CFG_OWN_GPIO(own))
@@ -318,7 +320,7 @@ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
/* GPIO Interrupt */ -#define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ +#define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, DRIVER)
/* @@ -326,22 +328,22 @@ * Both TX and RX are disabled. RX disabling is done to avoid unnecessary * setting of GPI_STS. RX Level/Edge Trig Configuration set to disable */ -#define PAD_NC(pad, pull) \ +#define PAD_NC(pad, pull) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \ - PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \ + PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS)
-#define PAD_CFG_GPI_APIC(pad, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ +#define PAD_CFG_GPI_APIC(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(IOAPIC, LEVEL, NONE), PAD_PULL(pull))
-#define PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ +#define PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(IOAPIC, LEVEL, INVERT), PAD_PULL(pull))
#define PAD_CFG_GPI_ACPI_SCI(pad, pull, rst, inv) \ @@ -360,18 +362,18 @@
#else /* General purpose input, routed to APIC */ -#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) #endif
/* General purpose input, routed to APIC - with IOStandby Config*/ -#define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
/* @@ -379,47 +381,47 @@ * on its own end. One just needs to pass an active high message into the * ITSS. */ -#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \ +#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \ PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT)
-#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ +#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE)
-#define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \ +#define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \ PAD_CFG_GPI_APIC(pad, pull, rst, EDGE_SINGLE, INVERT)
/* General purpose input, routed to SMI */ -#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE))
/* General purpose input, routed to SMI */ -#define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
-#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \ +#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \ PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT)
-#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \ +#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \ PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE)
/* General purpose input, routed to SCI */ -#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE))
/* General purpose input, routed to SCI */ -#define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \ @@ -428,33 +430,33 @@ #define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \ PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE)
-#define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \ - _PAD_CFG_STRUCT_3(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \ + _PAD_CFG_STRUCT_3(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE), PAD_CFG2_DEBEN | PAD_CFG2_##dur)
-#define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \ +#define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \ PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, INVERT, dur)
-#define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \ +#define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \ PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, NONE, dur)
/* General purpose input, routed to NMI */ -#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE))
#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) -#define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ +#define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
-#define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \ +#define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \ PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI)
#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/gpio: do some fixes in code style ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41035/1/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/41035/1/src/soc/intel/common/block/... PS1, Line 397: PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ please, no space before tabs
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41035
to look at the new patch set (#2).
Change subject: soc/intel/gpio: do some fixes in code style ......................................................................
soc/intel/gpio: do some fixes in code style
Change-Id: Ib4b4c28153398b6275728b28bda90e527d97e823 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 96 insertions(+), 94 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41035/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/gpio: do some fixes in code style ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41035/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41035/2//COMMIT_MSG@7 PS2, Line 7: soc/intel/gpio: do some fixes in code style Fix coding style
Hello build bot (Jenkins), Paul Menzel, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41035
to look at the new patch set (#3).
Change subject: soc/intel/common/gpio_defs: fix code style ......................................................................
soc/intel/common/gpio_defs: fix code style
Change-Id: Ib4b4c28153398b6275728b28bda90e527d97e823 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 124 insertions(+), 116 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41035/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/common/gpio_defs: fix code style ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41035/3/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/41035/3/src/soc/intel/common/block/... PS3, Line 202: #define PAD_CFG_NF_1V8(pad, pull, rst, func) \ Macros with complex values should be enclosed in parentheses
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/common/gpio_defs: fix code style ......................................................................
Patch Set 3: Code-Review+1
Please test with BUILD_TIMELESS=1 or abuild --timeless that this does not result in any changes to the resulting coreboot.rom for a mainboard using this code. That way, you can be certain that this is just a cosmetic change 😄
Hello build bot (Jenkins), Paul Menzel, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41035
to look at the new patch set (#4).
Change subject: soc/intel/common/gpio_defs: fix code style ......................................................................
soc/intel/common/gpio_defs: fix code style
Change-Id: Ib4b4c28153398b6275728b28bda90e527d97e823 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 124 insertions(+), 116 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41035/4
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/common/gpio_defs: fix code style ......................................................................
Patch Set 4:
Patch Set 3: Code-Review+1
Please test with BUILD_TIMELESS=1 or abuild --timeless that this does not result in any changes to the resulting coreboot.rom for a mainboard using this code. That way, you can be certain that this is just a cosmetic change 😄
Yes, this test was successful. Both images are no different. Thx
Hello build bot (Jenkins), Paul Menzel, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41035
to look at the new patch set (#5).
Change subject: soc/intel/common/gpio_defs: fix code style ......................................................................
soc/intel/common/gpio_defs: fix code style
Change-Id: Ib4b4c28153398b6275728b28bda90e527d97e823 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 124 insertions(+), 115 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41035/5
Hello build bot (Jenkins), Paul Menzel, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41035
to look at the new patch set (#6).
Change subject: soc/intel/common/gpio_defs: fix coding style ......................................................................
soc/intel/common/gpio_defs: fix coding style
Change-Id: Ib4b4c28153398b6275728b28bda90e527d97e823 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 124 insertions(+), 115 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41035/6
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/common/gpio_defs: fix coding style ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41035/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41035/2//COMMIT_MSG@7 PS2, Line 7: soc/intel/gpio: do some fixes in code style
Fix coding style
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/common/gpio_defs: fix coding style ......................................................................
Patch Set 6: Code-Review+1
Patch Set 4:
Patch Set 3: Code-Review+1
Please test with BUILD_TIMELESS=1 or abuild --timeless that this does not result in any changes to the resulting coreboot.rom for a mainboard using this code. That way, you can be certain that this is just a cosmetic change 😄
Yes, this test was successful. Both images are no different. Thx
Please report so in the commit message, e.g.:
Tested with BUILD_TIMELESS=1, <insert mainboard name here> does not change.
Hello build bot (Jenkins), Paul Menzel, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41035
to look at the new patch set (#7).
Change subject: soc/intel/common/gpio_defs: fix coding style ......................................................................
soc/intel/common/gpio_defs: fix coding style
Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard does not change.
Change-Id: Ib4b4c28153398b6275728b28bda90e527d97e823 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 124 insertions(+), 115 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41035/7
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/common/gpio_defs: fix coding style ......................................................................
Patch Set 7:
Patch Set 6: Code-Review+1
Patch Set 4:
Patch Set 3: Code-Review+1
Please test with BUILD_TIMELESS=1 or abuild --timeless that this does not result in any changes to the resulting coreboot.rom for a mainboard using this code. That way, you can be certain that this is just a cosmetic change 😄
Yes, this test was successful. Both images are no different. Thx
Please report so in the commit message, e.g.:
Tested with BUILD_TIMELESS=1, <insert mainboard name here> does not change.
Done
Hello build bot (Jenkins), Paul Menzel, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41035
to look at the new patch set (#9).
Change subject: soc/intel/common/gpio_defs: Fix coding style ......................................................................
soc/intel/common/gpio_defs: Fix coding style
Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard does not change.
Change-Id: Ib4b4c28153398b6275728b28bda90e527d97e823 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 124 insertions(+), 115 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41035/9
Hello build bot (Jenkins), Paul Menzel, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41035
to look at the new patch set (#11).
Change subject: soc/intel/common/gpio_defs: Fix coding style ......................................................................
soc/intel/common/gpio_defs: Fix coding style
Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard does not change.
Change-Id: Ib4b4c28153398b6275728b28bda90e527d97e823 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 125 insertions(+), 116 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41035/11
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/common/gpio_defs: Fix coding style ......................................................................
Patch Set 13: Code-Review+1
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/common/gpio_defs: Fix coding style ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41035/13/src/soc/intel/common/block... File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/41035/13/src/soc/intel/common/block... PS13, Line 155: hmm, not sure if using tabs here really makes it cleaner... I'd have used a single space here (and for all the others too) but that may be personal preference
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/common/gpio_defs: Fix coding style ......................................................................
Patch Set 13: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/41035/13/src/soc/intel/common/block... File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/41035/13/src/soc/intel/common/block... PS13, Line 155:
hmm, not sure if using tabs here really makes it cleaner... […]
The usual style is to align all those backslashes with tabs. However, the one on the first line is quite far away from the rest, so it doesn't matter if it's flying away from the rest. But we shall be consistent and use tabs everywhere
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/common/gpio_defs: Fix coding style ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41035/13/src/soc/intel/common/block... File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/41035/13/src/soc/intel/common/block... PS13, Line 155:
The usual style is to align all those backslashes with tabs. […]
Ack
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/common/gpio_defs: Fix coding style ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41035/13/src/soc/intel/common/block... File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/41035/13/src/soc/intel/common/block... PS13, Line 155:
Ack
Ack
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/common/gpio_defs: Fix coding style ......................................................................
Patch Set 14: Code-Review+1
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/common/gpio_defs: Fix coding style ......................................................................
Patch Set 16: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/common/gpio_defs: Fix coding style ......................................................................
Patch Set 16: Code-Review+2
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41035 )
Change subject: soc/intel/common/gpio_defs: Fix coding style ......................................................................
soc/intel/common/gpio_defs: Fix coding style
Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard does not change.
Change-Id: Ib4b4c28153398b6275728b28bda90e527d97e823 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41035 Reviewed-by: Andrey Petrov andrey.petrov@gmail.com Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 125 insertions(+), 116 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Andrey Petrov: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 1ff0b2c..e9abd00 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -133,7 +133,7 @@ #define PAD_CFG0_BUF_NO_DISABLE (0) #define PAD_CFG0_BUF_TX_DISABLE PAD_CFG0_TX_DISABLE #define PAD_CFG0_BUF_RX_DISABLE PAD_CFG0_RX_DISABLE -#define PAD_CFG0_BUF_TX_RX_DISABLE \ +#define PAD_CFG0_BUF_TX_RX_DISABLE \ (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE)
#define PAD_BUF(value) PAD_CFG0_BUF_##value @@ -146,17 +146,17 @@ #define PAD_IOSTERM(value) 0 #endif
-#define PAD_IRQ_CFG(route, trig, inv) \ - (PAD_IRQ_ROUTE(route) | \ - PAD_TRIG(trig) | \ - PAD_RX_POL(inv)) +#define PAD_IRQ_CFG(route, trig, inv) \ + (PAD_IRQ_ROUTE(route) | \ + PAD_TRIG(trig) | \ + PAD_RX_POL(inv))
#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) -#define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ - (PAD_IRQ_ROUTE(route1) | \ - PAD_IRQ_ROUTE(route2) | \ - PAD_TRIG(trig) | \ - PAD_RX_POL(inv)) +#define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ + (PAD_IRQ_ROUTE(route1) | \ + PAD_IRQ_ROUTE(route2) | \ + PAD_TRIG(trig) | \ + PAD_RX_POL(inv)) #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */
#define _PAD_CFG_STRUCT(__pad, __config0, __config1) \ @@ -180,121 +180,130 @@ #endif
/* Native function configuration */ -#define PAD_CFG_NF(pad, pull, rst, func) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxLASTRxE)) +#define PAD_CFG_NF(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
/* * Set native function with RX Level/Edge configuration and disable * input/output buffer if necessary */ -#define PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_TRIG(trig) | \ - PAD_BUF(bufdis) | PAD_FUNC(func), \ +#define PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(bufdis) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S Not applicable to all SOCs. Refer EDS */ -#define PAD_CFG_NF_1V8(pad, pull, rst, func) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) |\ - PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_TOL_1V8) +#define PAD_CFG_NF_1V8(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_TOL_1V8) #endif
/* Native function configuration for standby state */ -#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate)) +#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate))
/* Native function configuration for standby state, also configuring iostandby as masked */ -#define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(IGNORE)) +#define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(IGNORE))
/* Native function configuration for standby state, also configuring iosstate and iosterm */ -#define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ +#define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
/* Configure native function, iosstate, iosterm and disable input/output buffer */ #define PAD_CFG_NF_BUF_IOSSTATE_IOSTERM(pad, pull, rst, func, bufdis, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_BUF(bufdis) | PAD_FUNC(func), \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_BUF(bufdis) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
/* General purpose output, no pullup/down. */ -#define PAD_CFG_GPO(pad, val, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ +#define PAD_CFG_GPO(pad, val, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE))
/* General purpose output, with termination specified */ -#define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ +#define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
/* General purpose output, no pullup/down. */ -#define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ - PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG_OWN_GPIO(DRIVER)) +#define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | \ + PAD_CFG_OWN_GPIO(DRIVER))
/* General purpose output. */ #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm))
/* General purpose input */ -#define PAD_CFG_GPI(pad, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ +#define PAD_CFG_GPI(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
-#define PAD_CFG_GPI_IOSSTATE(pad, pull, rst, iosstate) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ +#define PAD_CFG_GPI_IOSSTATE(pad, pull, rst, iosstate) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate))
-#define PAD_CFG_GPI_IOSSTATE_IOSTERM(pad, pull, rst, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ +#define PAD_CFG_GPI_IOSSTATE_IOSTERM(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
/* * General purpose input. The following macro sets the * Host Software Pad Ownership to GPIO Driver mode. */ -#define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) \ - _PAD_CFG_STRUCT(pad, PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ +#define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE) | PAD_CFG_OWN_GPIO(own))
-#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ +#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | PAD_IOSSTATE(TxDRxE))
-#define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ +#define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
-#define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ +#define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
/* GPIO Interrupt */ -#define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ +#define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, DRIVER)
/* @@ -302,22 +311,22 @@ * Both TX and RX are disabled. RX disabling is done to avoid unnecessary * setting of GPI_STS. RX Level/Edge Trig Configuration set to disable */ -#define PAD_NC(pad, pull) \ +#define PAD_NC(pad, pull) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \ - PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \ + PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS)
-#define PAD_CFG_GPI_APIC(pad, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ +#define PAD_CFG_GPI_APIC(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(IOAPIC, LEVEL, NONE), PAD_PULL(pull))
-#define PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ +#define PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(IOAPIC, LEVEL, INVERT), PAD_PULL(pull))
#define PAD_CFG_GPI_ACPI_SCI(pad, pull, rst, inv) \ @@ -336,18 +345,18 @@
#else /* General purpose input, routed to APIC */ -#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) #endif
/* General purpose input, routed to APIC - with IOStandby Config*/ -#define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
/* @@ -355,47 +364,47 @@ * on its own end. One just needs to pass an active high message into the * ITSS. */ -#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \ +#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \ PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT)
-#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ +#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE)
-#define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \ +#define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \ PAD_CFG_GPI_APIC(pad, pull, rst, EDGE_SINGLE, INVERT)
/* General purpose input, routed to SMI */ -#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE))
/* General purpose input, routed to SMI */ -#define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
-#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \ +#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \ PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT)
-#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \ +#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \ PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE)
/* General purpose input, routed to SCI */ -#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE))
/* General purpose input, routed to SCI */ -#define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \ @@ -404,33 +413,33 @@ #define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \ PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE)
-#define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \ - _PAD_CFG_STRUCT_3(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \ + _PAD_CFG_STRUCT_3(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE), PAD_CFG2_DEBEN | PAD_CFG2_##dur)
-#define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \ +#define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \ PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, INVERT, dur)
-#define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \ +#define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \ PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, NONE, dur)
/* General purpose input, routed to NMI */ -#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ +#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE))
#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) -#define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ +#define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
-#define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \ +#define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \ PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI)
#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */