David Milosevic has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83979?usp=email )
Change subject: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support ......................................................................
[WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support
This patch adds support for the odroid-h4 board. Note, that this is still a work in progress and was not yet properly tested on real hardware.
Change-Id: I7e0d395ba3d15dfcf6d47a222b90499ca371e4eb Signed-off-by: David Milosevic David.Milosevic@9elements.com --- A src/mainboard/hardkernel/Kconfig A src/mainboard/hardkernel/Kconfig.name A src/mainboard/hardkernel/odroid-h4/Kconfig A src/mainboard/hardkernel/odroid-h4/Kconfig.name A src/mainboard/hardkernel/odroid-h4/Makefile.mk A src/mainboard/hardkernel/odroid-h4/board_info.txt A src/mainboard/hardkernel/odroid-h4/bootblock.c A src/mainboard/hardkernel/odroid-h4/data.vbt A src/mainboard/hardkernel/odroid-h4/devicetree.cb A src/mainboard/hardkernel/odroid-h4/dsdt.asl A src/mainboard/hardkernel/odroid-h4/gpio.h A src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c 12 files changed, 572 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/83979/1
diff --git a/src/mainboard/hardkernel/Kconfig b/src/mainboard/hardkernel/Kconfig new file mode 100644 index 0000000..eff82b2 --- /dev/null +++ b/src/mainboard/hardkernel/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_HARDKERNEL + +choice + prompt "Mainboard model" + +source "src/mainboard/hardkernel/*/Kconfig.name" + +endchoice + +source "src/mainboard/hardkernel/*/Kconfig" + +config MAINBOARD_VENDOR + default "Hardkernel" + +endif # VENDOR_HARDKERNEL diff --git a/src/mainboard/hardkernel/Kconfig.name b/src/mainboard/hardkernel/Kconfig.name new file mode 100644 index 0000000..ff0f70d --- /dev/null +++ b/src/mainboard/hardkernel/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config VENDOR_HARDKERNEL + bool "Hardkernel" diff --git a/src/mainboard/hardkernel/odroid-h4/Kconfig b/src/mainboard/hardkernel/odroid-h4/Kconfig new file mode 100644 index 0000000..cc4cda4 --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/Kconfig @@ -0,0 +1,48 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_HARDKERNEL_ODROID_H4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_GENERIC + select DRIVERS_INTEL_DPTF + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select FSP_TYPE_IOT + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SUPERIO_ITE_IT8613E + select DRIVERS_UART_8250IO + select USE_LEGACY_8254_TIMER + select SOC_INTEL_ALDERLAKE_PCH_N + +config MAINBOARD_DIR + default "hardkernel/odroid-h4" + +config MAINBOARD_PART_NUMBER + default "Odroid H4" + +config MAINBOARD_FAMILY + string + default "HARDKERNEL_ODROID_H4" + +config PCIEXP_ASPM + default y + +# Setting this makes NVMe SSD not work +config PCIEXP_L1_SUB_STATE + default n + +# Setting this makes 2.5Gb NICs not work +config PCIEXP_CLK_PM + default n + +# This platform has limited means to display POST codes +config NO_POST + default y + +endif #BOARD_HARDKERNEL_ODROID_H4 diff --git a/src/mainboard/hardkernel/odroid-h4/Kconfig.name b/src/mainboard/hardkernel/odroid-h4/Kconfig.name new file mode 100644 index 0000000..9ee3959 --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_HARDKERNEL_ODROID_H4 + bool "Odroid H4" diff --git a/src/mainboard/hardkernel/odroid-h4/Makefile.mk b/src/mainboard/hardkernel/odroid-h4/Makefile.mk new file mode 100644 index 0000000..72915ef --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += romstage_fsp_params.c diff --git a/src/mainboard/hardkernel/odroid-h4/board_info.txt b/src/mainboard/hardkernel/odroid-h4/board_info.txt new file mode 100644 index 0000000..1dac1ec --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Hardkernel +Board name: Odroid H4 +Board URL: TODO +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2024 diff --git a/src/mainboard/hardkernel/odroid-h4/bootblock.c b/src/mainboard/hardkernel/odroid-h4/bootblock.c new file mode 100644 index 0000000..d494f9a --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/bootblock.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8613e/it8613e.h> + +#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) + +void bootblock_mainboard_early_init(void) +{ + /* Set up GPIOs on Super I/O. */ + ite_reg_write(GPIO_DEV, 0x25, 0x01); // Enable Pin GP10 + ite_reg_write(GPIO_DEV, 0x27, 0x02); // Enable Pin GP31 + ite_reg_write(GPIO_DEV, 0x28, 0x01); // Enable Pin GP40 + ite_reg_write(GPIO_DEV, 0x29, 0x01); // Enable Pin GP50 + ite_reg_write(GPIO_DEV, 0x2c, 0x41); // Internal Voltage Divider for ACC3 + ite_reg_write(GPIO_DEV, 0xbc, 0xc0); // GP56, GP57 Internal pullup + ite_reg_write(GPIO_DEV, 0xbd, 0x03); // GP60, GP61 Internal pullup + ite_reg_write(GPIO_DEV, 0xc3, 0x41); // GP40, GP46 Simple I/O function + ite_set_3vsbsw(GPIO_DEV, true); + ite_delay_pwrgd3(GPIO_DEV); +} + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/hardkernel/odroid-h4/data.vbt b/src/mainboard/hardkernel/odroid-h4/data.vbt new file mode 100644 index 0000000..f25d9d9 --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/data.vbt Binary files differ diff --git a/src/mainboard/hardkernel/odroid-h4/devicetree.cb b/src/mainboard/hardkernel/odroid-h4/devicetree.cb new file mode 100644 index 0000000..2b7e5b5 --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/devicetree.cb @@ -0,0 +1,170 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/alderlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + register "sagv" = "SaGv_Enabled" + + register "dptf_enable" = "1" + + register "s0ix_enable" = "1" + + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + }" + + # TODO: Configure external V1P05/Vnn/VnnSx Rails + #register "ext_fivr_settings" = "{ + # .configure_ext_fivr = 1, + # .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, + # .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + # .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + # .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + # .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, + # .v1p05_voltage_mv = 1050, + # .vnn_voltage_mv = 780, + # .vnn_sx_voltage_mv = 1050, + # .v1p05_icc_max_ma = 500, + # .vnn_icc_max_ma = 500, + #}" + + device domain 0 on + device ref igpu on + register "ddi_portA_config" = "1" + register "ddi_portB_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + end + device ref dtt on end + device ref crashlog off end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)" # USB3/2 Type A upper + end + #device ref xhci on + # register "usb2_ports" = "{ + # [0] = USB2_PORT_TYPE_C(OC0), /* Type-C */ + # [1] = USB2_PORT_MID(OC_SKIP), /* microSD card reader */ + # [2] = USB2_PORT_MID(OC3), /* USB2 Type A upper */ + # [3] = USB2_PORT_MID(OC3), /* USB2 Type A lower */ + # [4] = USB2_PORT_MID(OC3), /* USB3/2 Type A upper */ + # [5] = USB2_PORT_MID(OC3), /* USB3/2 Type A lower */ + # [7] = USB2_PORT_MID(OC_SKIP), /* M.2 WLAN */ + # }" + + # register "usb3_ports" = "{ + # [0] = USB3_PORT_DEFAULT(OC0), /* Type-C */ + # [1] = USB3_PORT_DEFAULT(OC_SKIP), /* microSD card reader */ + # [5] = USB3_PORT_DEFAULT(OC3), /* USB3/2 Type A lower */ + # [6] = USB3_PORT_DEFAULT(OC3), /* USB3/2 Type A upper */ + # }" + #end + device ref i2c0 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + end + device ref i2c1 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref sata off end + #device ref pcie_rp3 on + # register "pch_pcie_rp[PCH_RP(3)]" = "{ + # .clk_src = 2, + # .clk_req = 2, + # .flags = PCIE_RP_CLK_REQ_DETECT, + # }" + # smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + # "M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth2X" + #end + #device ref pcie_rp7 on # LAN1 + # register "pch_pcie_rp[PCH_RP(7)]" = "{ + # .clk_src = 3, + # .clk_req = 3, + # .flags = PCIE_RP_CLK_REQ_DETECT, + # }" + #end + #device ref pcie_rp9 on # LAN2 + # register "pch_pcie_rp[PCH_RP(9)]" = "{ + # .clk_src = 0, + # .clk_req = 0, + # .flags = PCIE_RP_CLK_REQ_DETECT, + # }" + #end + #device ref pcie_rp10 on + # register "pch_pcie_rp[PCH_RP(10)]" = "{ + # .clk_src = 1, + # .clk_req = 1, + # .flags = PCIE_RP_CLK_REQ_DETECT, + # }" + # smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + # "M.2/E 2230 (M2_WIFI1)" "SlotDataBusWidth1X" + #end + device ref pch_espi on + # Needed for ITE SuperIO + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x000c03e1" + register "gen4_dec" = "0x001c02e1" + chip superio/ite/it8613e + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "ec.vin_mask" = "VIN_ALL" + # FAN1 + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" + register "FAN2.smart.tmpin" = " 1" + register "FAN2.smart.tmp_off" = "32" + register "FAN2.smart.tmp_start" = "35" + register "FAN2.smart.tmp_full" = "96" + register "FAN2.smart.tmp_delta" = " 1" + register "FAN2.smart.pwm_start" = "30" + register "FAN2.smart.slope" = " 1" + + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on end # COM 1 + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa30 + io 0x62 = 0xa20 + irq 0x70 = 0x00 + end + device pnp 2e.5 on end # Keyboard + device pnp 2e.6 on end # Mouse + device pnp 2e.7 on # GPIO + io 0x60 = 0xa10 + io 0x62 = 0xa00 + irq 0x70 = 0x00 + irq 0x71 = 0x01 + end + device pnp 2e.a on end # CIR + end + end + device ref uart0 on + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + }" + end + device ref gspi0 on + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + }" + end + device ref ish on end + device ref hda on + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + end + device ref smbus on end + end +end diff --git a/src/mainboard/hardkernel/odroid-h4/dsdt.asl b/src/mainboard/hardkernel/odroid-h4/dsdt.asl new file mode 100644 index 0000000..58c147e --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <gpio.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + #include <soc/intel/alderlake/acpi/tcss.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/hardkernel/odroid-h4/gpio.h b/src/mainboard/hardkernel/odroid-h4/gpio.h new file mode 100644 index 0000000..019ca52 --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/gpio.h @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +/* Pad configuration was created using odroid schematics (put link here) */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */ + PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* VRALERT# */ + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_CFG_GPI(GPP_B8, NONE, DEEP), + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), /* PMCALERT# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */ + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), /* SPKR */ + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B23, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* ESPI_IO0 */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* ESPI_IO1 */ + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* ESPI_IO2 */ + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* ESPI_IO3 */ + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* ESPI_CS0# */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* ESPI_ALERT0# */ + PAD_NC(GPP_A6, NONE), + PAD_NC(GPP_A7, NONE), + PAD_CFG_GPO(GPP_A8, 1, PLTRST), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* ESPI_CLK */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* ESPI_RESET# */ + PAD_NC(GPP_A11, NONE), + PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), /* SATAXPCIE1 */ + PAD_NC(GPP_A13, NONE), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* USB_OC1# */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* USB_OC2# */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* USB_OC3# */ + PAD_NC(GPP_A17, NONE), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DDSP_HPDB */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* DDSP_HPD1 */ + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_I ------- */ + PAD_NC(GPP_I5, NONE), + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* EMMC_DATA0 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), /* EMMC_DATA1 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), /* EMMC_DATA2 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), /* EMMC_DATA3 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), /* EMMC_DATA4 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), /* EMMC_DATA5 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), /* EMMC_DATA6 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), /* EMMC_DATA7 */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), /* EMMC_RCLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), /* EMMC_CLK */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), /* EMMC_RESET# */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_NC(GPP_H0, NONE), + PAD_NC(GPP_H1, NONE), + PAD_NC(GPP_H2, NONE), + PAD_NC(GPP_H3, NONE), + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* I2C0_SDA */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), /* I2C0_SCL */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* I2C1_SDA */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* I2C1_SCL */ + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_NC(GPP_H10, NONE), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0_TXD */ + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* PROC_C10_GATE# */ + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* SRCCLKREQ0# */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* SRCCLKREQ1# */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* SRCCLKREQ2# */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* SRCCLKREQ3# */ + PAD_NC(GPP_D9, NONE), + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), /* DDP3_CTRLDATA */ + PAD_NC(GPP_D11, NONE), + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF5), /* BSSB_LS3_TX */ + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* BATLOW# */ + PAD_CFG_NF(GPD1, NONE, PWROK, NF1), /* ACPRESENT */ + PAD_NC(GPD2, NONE), + PAD_CFG_NF(GPD3, NONE, PWROK, NF1), /* PWRBTN# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* SLP_A# */ + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */ + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */ + PAD_NC(GPD11, NONE), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ + PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), /* SMBALERT# */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0DATA */ + PAD_NC(GPP_C5, NONE), + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), /* SML1CLK */ + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), /* SML1DATA */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_BRI_DT */ + PAD_NC(GPP_F1, NONE), + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* CNV_RGI_DT */ + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_NC(GPP_F7, NONE), + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + PAD_NC(GPP_E7, NONE), + PAD_NC(GPP_E8, NONE), + PAD_NC(GPP_E9, NONE), + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDSP_HPDA */ + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_NC(GPP_E17, NONE), + PAD_NC(GPP_E18, NONE), /* TODO */ + PAD_NC(GPP_E19, NONE), /* TODO */ + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), /* DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), /* DDPA_CTRLDATA */ + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), /* HDA_BCLK */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), /* HDA_SYNC */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1), /* HDA_SDO */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* HDA_SDI0 */ + PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1), /* HDA_RST# */ + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c b/src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c new file mode 100644 index 0000000..1477bc0 --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <soc/meminit.h> + +#include "gpio.h" + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + /* According to DOC #573387 rcomp values no longer have to be provided */ + /* DDR DIMM configuration does not need to set DQ/DQS maps */ + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .LpDdrDqDqsReTraining = 1, + + .ddr_config = { + .dq_pins_interleaved = false, + }, +}; + +static const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus[0] = { .addr_dimm[0] = 0x50, }, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + /* + * Alder Lake common meminit block driver considers bus width to be 128-bit and + * populates the meminit data accordingly. Alder Lake-N has single memory controller + * with 64-bit bus width. By setting half_populated to true, only the bottom half is + * populated. + * TODO: Implement __weak variant_is_half_populated(void) function. + */ + const bool half_populated = true; + + memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, half_populated); + + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +}