[M] Change in coreboot[master]: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config

[Eric Lai (Code Review)]

Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75756?usp=email )

Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
......................................................................

arch/x86: Introduce DUMP_SMBIOS_TYPE17 config

DDR5 spd is not supported read by coreboot. But FSP can read it,
so print the memory information from smbios type17 dimm information.

TEST=check the coreboot log.
memory Channel-0-DIMM-0 type is DDR5
memory part number is M425R1GB4BB0-CQKOL
memory speed is 4800 MT/s
memory size is 8192 MiB

Signed-off-by: Eric Lai 
Change-Id: I2b5ca1f4a59598531a6cba500672c2717f2a7b00
---
M src/arch/x86/Kconfig
M src/arch/x86/smbios.c
2 files changed, 64 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/75756/1

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index b3cf96b..9c85a49 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -359,4 +359,9 @@
    help
       Size of reserved space for EC firmware pointer

+config DUMP_SMBIOS_TYPE17
+	bool
+	default n
+	help
+	   Dump part of SMBIOS type17 dimm information.
 endif
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index 1ec0ad2..2fd3f18 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -219,6 +219,62 @@
    t->serial_number = smbios_add_string(t->eos, serial);
 }

+static const char *memory_device_type(u8 code)
+{
+	/* 7.18.2 */
+	static const char *type[] = {
+		"Other", /* 0x01 */
+		"Unknown",
+		"DRAM",
+		"EDRAM",
+		"VRAM",
+		"SRAM",
+		"RAM",
+		"ROM",
+		"Flash",
+		"EEPROM",
+		"FEPROM",
+		"EPROM",
+		"CDRAM",
+		"3DRAM",
+		"SDRAM",
+		"SGRAM",
+		"RDRAM",
+		"DDR",
+		"DDR2",
+		"DDR2 FB-DIMM",
+		"Reserved",
+		"Reserved",
+		"Reserved",
+		"DDR3",
+		"FBD2",
+		"DDR4",
+		"LPDDR",
+		"LPDDR2",
+		"LPDDR3",
+		"LPDDR4",
+		"Logical non-volatile device",
+		"HBM",
+		"HBM2",
+		"DDR5",
+		"LPDDR5" /* 0x23 */
+	};
+
+	if (code >= 0x01 && code <= 0x23)
+		return type[code - 0x01];
+	return "Unsupported memory type";
+}
+
+static void dump_smbios_type17(struct dimm_info *dimm)
+{
+	printk(BIOS_INFO, "memory Channel-%d-DIMM-%d", dimm->channel_num, dimm->dimm_num);
+	printk(BIOS_INFO, " type is %s\n", memory_device_type(dimm->ddr_type));
+	printk(BIOS_INFO, "memory part number is %s\n", dimm->module_part_number);
+	printk(BIOS_INFO, "memory speed is %d MT/s\n",
+					dimm->configured_speed_mts ? : dimm->ddr_frequency);
+	printk(BIOS_INFO, "memory size is %d MiB\n", dimm->dimm_size);
+}
+
 static int create_smbios_type17_for_dimm(struct dimm_info *dimm,
    				 unsigned long *current, int *handle,
    				 int type16_handle)
@@ -273,6 +329,9 @@
    t->phys_memory_array_handle = type16_handle;

*handle += 1;
+	if(CONFIG(DUMP_SMBIOS_TYPE17))
+		dump_smbios_type17(dimm);
+
    return smbios_full_table_len(&t->header, t->eos);
 }