[S] Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Fix source clock check condition fo...
Attention is currently required from: Bora Guvendik, Hannah Williams, Anil Kumar K, Cliff Huang, Tarun Tuli.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73889 )
Change subject: soc/intel/common/block/pcie/rtd3: Fix source clock check condition for PM method ......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/73889/comment/3cf2c14d_3a58b424 PS3, Line 9: srcclk_pin is 0-based and '0' is a valid clock source number. : If srcclk_pin is set to -1, then the clock will not be disabled in D3. : Therefore, clock source gating method should not be generated. Please do not wrap lines just because the sentence ends.
https://review.coreboot.org/c/coreboot/+/73889/comment/ed0de1f3_424a708d PS3, Line 16: expected What device did you test with? On what device is the pin 0 or -1, so the entries were incorrect?
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Paul Menzel (Code Review)