Hello Chris Wang, Eric Peers,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/42215
to review the following change.
Change subject: Add xhci0_force_gen1 parameter to AGESA FSP-S UPD ......................................................................
Add xhci0_force_gen1 parameter to AGESA FSP-S UPD
add xhci0_force_gen1 parameter for force xhci0 to gen1
BUG=b:156314787 BRANCH=trembyle-bringup TEST=Build, verified the device speed been forced to gen 1 on Trembyle.
Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Change-Id: Iae601ae595827d7edfb99445f896f59fb136d88b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+... Reviewed-by: Eric Peers epeers@google.com Commit-Queue: Eric Peers epeers@google.com Tested-by: Eric Peers epeers@google.com --- M src/vendorcode/amd/fsp/picasso/FspsUpd.h 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/42215/1
diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index 66ea60b..afc06e1 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -44,7 +44,8 @@ /** Offset 0x00EC**/ uint8_t fch_usb_early_debug_select_enable; /** Offset 0x00ED**/ uint8_t unused8; /** Offset 0x00EE**/ uint32_t xhci_oc_pin_select; - /** Offset 0x00F2**/ uint8_t UnusedUpdSpace0[46]; + /** Offset 0x00F2**/ uint8_t xhci0_force_gen1; + /** Offset 0x00F3**/ uint8_t UnusedUpdSpace0[45]; /** Offset 0x0120**/ uint16_t UpdTerminator; } FSP_S_CONFIG;
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42215 )
Change subject: Add xhci0_force_gen1 parameter to AGESA FSP-S UPD ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42215/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42215/1//COMMIT_MSG@7 PS1, Line 7: Add xhci0_force_gen1 parameter to AGESA FSP-S UPD Please add a prefix.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42215 )
Change subject: Add xhci0_force_gen1 parameter to AGESA FSP-S UPD ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42215/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42215/1//COMMIT_MSG@13 PS1, Line 13: TEST=Build, verified the device speed been forced to gen 1 on Trembyle. How did you verify that?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42215 )
Change subject: Add xhci0_force_gen1 parameter to AGESA FSP-S UPD ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42215/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42215/1//COMMIT_MSG@9 PS1, Line 9: add xhci0_force_gen1 parameter for force xhci0 to gen1 Please start with a capital letter and add a dot/period at the end.
https://review.coreboot.org/c/coreboot/+/42215/1//COMMIT_MSG@10 PS1, Line 10: Is there only one xHCI controller?
Hello build bot (Jenkins), Furquan Shaikh, Chris Wang, Eric Peers,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42215
to look at the new patch set (#2).
Change subject: Add xhci0_force_gen1 parameter to AGESA FSP-S UPD ......................................................................
Add xhci0_force_gen1 parameter to AGESA FSP-S UPD
To add xhci0_force_gen1 parameter for force xhci0 to gen1.
BUG=b:156314787 BRANCH=trembyle-bringup TEST=Build, verified with the gen2 device and the speed been forced to gen1 on Trembyle.
Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Change-Id: Iae601ae595827d7edfb99445f896f59fb136d88b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+... Reviewed-by: Eric Peers epeers@google.com Commit-Queue: Eric Peers epeers@google.com Tested-by: Eric Peers epeers@google.com --- M src/vendorcode/amd/fsp/picasso/FspsUpd.h 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/42215/2
Hello build bot (Jenkins), Furquan Shaikh, Chris Wang, Eric Peers,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42215
to look at the new patch set (#3).
Change subject: vc/amd/fsp/picasso:Add xhci0_force_gen1 parameter to AGESA FSP-S UPD ......................................................................
vc/amd/fsp/picasso:Add xhci0_force_gen1 parameter to AGESA FSP-S UPD
To add xhci0_force_gen1 parameter for force xhci0 to gen1.
BUG=b:156314787 BRANCH=trembyle-bringup TEST=Build, verified with the gen2 device and the speed been forced to gen1 on Trembyle.
Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Change-Id: Iae601ae595827d7edfb99445f896f59fb136d88b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+... Reviewed-by: Eric Peers epeers@google.com Commit-Queue: Eric Peers epeers@google.com Tested-by: Eric Peers epeers@google.com --- M src/vendorcode/amd/fsp/picasso/FspsUpd.h 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/42215/3
chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42215 )
Change subject: vc/amd/fsp/picasso:Add xhci0_force_gen1 parameter to AGESA FSP-S UPD ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/42215/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42215/1//COMMIT_MSG@7 PS1, Line 7: Add xhci0_force_gen1 parameter to AGESA FSP-S UPD
Please add a prefix.
Done
https://review.coreboot.org/c/coreboot/+/42215/1//COMMIT_MSG@9 PS1, Line 9: add xhci0_force_gen1 parameter for force xhci0 to gen1
Please start with a capital letter and add a dot/period at the end.
Done
https://review.coreboot.org/c/coreboot/+/42215/1//COMMIT_MSG@10 PS1, Line 10:
Is there only one xHCI controller?
only for xhci0
https://review.coreboot.org/c/coreboot/+/42215/1//COMMIT_MSG@13 PS1, Line 13: TEST=Build, verified the device speed been forced to gen 1 on Trembyle.
How did you verify that?
verified with a USB3 Gen2 device and check the speed was been limited to Gen1.
Eric Peers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42215 )
Change subject: vc/amd/fsp/picasso:Add xhci0_force_gen1 parameter to AGESA FSP-S UPD ......................................................................
Patch Set 3: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42215 )
Change subject: vc/amd/fsp/picasso:Add xhci0_force_gen1 parameter to AGESA FSP-S UPD ......................................................................
Patch Set 3: Code-Review+2
chris wang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/42215 )
Change subject: vc/amd/fsp/picasso:Add xhci0_force_gen1 parameter to AGESA FSP-S UPD ......................................................................
Abandoned
CL:42529 had included this change
-
chris wang (Code Review) -
Eric Peers (Code Review)
-
Furquan Shaikh (Code Review)
-
Paul Menzel (Code Review)