Change in coreboot[master]: soc/amd/cezanne: Correct S0i3 verstage softfuse bit

[Rob Barnes (Code Review)]

Attention is currently required from: Raul Rangel, Rob Barnes, Karthik Ramasubramanian, Felix Held.
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Karthik Ramasubramanian, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/60214

to look at the new patch set (#2).

Change subject: soc/amd/cezanne: Correct S0i3 verstage softfuse bit
......................................................................

soc/amd/cezanne: Correct S0i3 verstage softfuse bit

PSP_S0I3_RESUME_VERSTAGE softfuse bit is 58, not 40.

BUG=b:202397678
BRANCH=None
TEST=Boot guybrush, ensure S0i3 verstage runs with latest PSP.

Change-Id: Ia27f6e48e345aac0d5f6579d663a6b655688239a
Signed-off-by: Rob Barnes 
---
M src/soc/amd/cezanne/Makefile.inc
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/60214/2