Hello Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/45710
to review the following change.
Change subject: x86: Add a fake SoC along with a board for build testing ......................................................................
x86: Add a fake SoC along with a board for build testing
This fake SoC code should serve as a minimal example how a buildable code base can look like.
Starting with a buildable commit should help with the review of the actual code, and also avoid any regressions when common coreboot code changes.
As the fake code itself is build-tested, it should advance with coreboot and can't rot like documentation might.
Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112 Signed-off-by: Nico Huber nico.h@gmx.de --- A src/mainboard/fake/Kconfig A src/mainboard/fake/Kconfig.name A src/mainboard/fake/x86/Kconfig A src/mainboard/fake/x86/Kconfig.name A src/mainboard/fake/x86/board_info.txt A src/mainboard/fake/x86/devicetree.cb A src/soc/fake/Kconfig A src/soc/fake/x86/Kconfig A src/soc/fake/x86/Makefile.inc A src/soc/fake/x86/cache_as_ram.S A src/soc/fake/x86/chip.c A src/soc/fake/x86/exit_car.S A src/soc/fake/x86/romstage.c A src/soc/fake/x86/timer.c 14 files changed, 126 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45710/1
diff --git a/src/mainboard/fake/Kconfig b/src/mainboard/fake/Kconfig new file mode 100644 index 0000000..2c0431a --- /dev/null +++ b/src/mainboard/fake/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_FAKE + +choice + prompt "Mainboard model" + +source "src/mainboard/fake/*/Kconfig.name" + +endchoice + +source "src/mainboard/fake/*/Kconfig" + +config MAINBOARD_VENDOR + default "Fake" + +endif # VENDOR_FAKE diff --git a/src/mainboard/fake/Kconfig.name b/src/mainboard/fake/Kconfig.name new file mode 100644 index 0000000..3beb2c0a --- /dev/null +++ b/src/mainboard/fake/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_FAKE + bool "Fake boards for build testing only" diff --git a/src/mainboard/fake/x86/Kconfig b/src/mainboard/fake/x86/Kconfig new file mode 100644 index 0000000..db0746b --- /dev/null +++ b/src/mainboard/fake/x86/Kconfig @@ -0,0 +1,15 @@ +if MAINBOARD_FAKE_X86 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_FAKE_X86 + select MISSING_BOARD_RESET + select BOARD_ROMSIZE_KB_256 # MTRR code minimum + +config MAINBOARD_DIR + default "fake/x86" + +config MAINBOARD_PART_NUMBER + default "Fake86" + +endif diff --git a/src/mainboard/fake/x86/Kconfig.name b/src/mainboard/fake/x86/Kconfig.name new file mode 100644 index 0000000..a579d03 --- /dev/null +++ b/src/mainboard/fake/x86/Kconfig.name @@ -0,0 +1,9 @@ +config MAINBOARD_FAKE_X86 + bool "x86 fake board" + help + This fake mainboard along with the fake/x86 SoC should serve + as a minimal example how a buildable code base can look like. + + Starting with a buildable commit should help with the review + of the actual code, and also avoid any regressions when common + coreboot code changes. diff --git a/src/mainboard/fake/x86/board_info.txt b/src/mainboard/fake/x86/board_info.txt new file mode 100644 index 0000000..c778859 --- /dev/null +++ b/src/mainboard/fake/x86/board_info.txt @@ -0,0 +1 @@ +Category: misc diff --git a/src/mainboard/fake/x86/devicetree.cb b/src/mainboard/fake/x86/devicetree.cb new file mode 100644 index 0000000..38e82bd --- /dev/null +++ b/src/mainboard/fake/x86/devicetree.cb @@ -0,0 +1,6 @@ +chip soc/fake/x86 + + device domain 0 on + end + +end diff --git a/src/soc/fake/Kconfig b/src/soc/fake/Kconfig new file mode 100644 index 0000000..b498e7c --- /dev/null +++ b/src/soc/fake/Kconfig @@ -0,0 +1 @@ +source "src/soc/fake/*/Kconfig" diff --git a/src/soc/fake/x86/Kconfig b/src/soc/fake/x86/Kconfig new file mode 100644 index 0000000..686a8d5 --- /dev/null +++ b/src/soc/fake/x86/Kconfig @@ -0,0 +1,26 @@ +config SOC_FAKE_X86 + bool + help + This fake SoC code should serve as a minimal example how a + buildable code base can look like. + + Starting with a buildable commit should help with the review + of the actual code, and also avoid any regressions when common + coreboot code changes. + +if SOC_FAKE_X86 + +config SOC_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 + select NO_MONOTONIC_TIMER + select NO_MMCONF_SUPPORT + select UNKNOWN_TSC_RATE + +config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld + default 0x100 + +endif diff --git a/src/soc/fake/x86/Makefile.inc b/src/soc/fake/x86/Makefile.inc new file mode 100644 index 0000000..0780607 --- /dev/null +++ b/src/soc/fake/x86/Makefile.inc @@ -0,0 +1,15 @@ +ifeq ($(CONFIG_SOC_FAKE_X86),y) + +bootblock-y += cache_as_ram.S +bootblock-y += ../../../cpu/intel/car/bootblock.c + +postcar-y += exit_car.S + +romstage-y += romstage.c + +ramstage-y += chip.c +ramstage-y += timer.c + +subdirs-y += ../../../cpu/x86/mtrr + +endif diff --git a/src/soc/fake/x86/cache_as_ram.S b/src/soc/fake/x86/cache_as_ram.S new file mode 100644 index 0000000..a350143 --- /dev/null +++ b/src/soc/fake/x86/cache_as_ram.S @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.global bootblock_pre_c_entry + +.code32 +bootblock_pre_c_entry: + call bootblock_c_entry_bist + +.Lhlt: + hlt + jmp .Lhlt diff --git a/src/soc/fake/x86/chip.c b/src/soc/fake/x86/chip.c new file mode 100644 index 0000000..a5ec309 --- /dev/null +++ b/src/soc/fake/x86/chip.c @@ -0,0 +1,3 @@ +#include <device/device.h> + +struct chip_operations soc_fake_x86_ops = { NULL }; diff --git a/src/soc/fake/x86/exit_car.S b/src/soc/fake/x86/exit_car.S new file mode 100644 index 0000000..0f1b227 --- /dev/null +++ b/src/soc/fake/x86/exit_car.S @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.global chipset_teardown_car + +.code32 +chipset_teardown_car: + /* Return to caller. */ + jmp *%esp diff --git a/src/soc/fake/x86/romstage.c b/src/soc/fake/x86/romstage.c new file mode 100644 index 0000000..91074b2 --- /dev/null +++ b/src/soc/fake/x86/romstage.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/cpu.h> + +asmlinkage void car_stage_entry(void) +{ +} diff --git a/src/soc/fake/x86/timer.c b/src/soc/fake/x86/timer.c new file mode 100644 index 0000000..9054ffd --- /dev/null +++ b/src/soc/fake/x86/timer.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> + +void init_timer(void) +{ +}
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45710 )
Change subject: x86: Add a fake SoC along with a board for build testing ......................................................................
Patch Set 1:
This is enlightening, thank you for going through the exercise Nico!
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45710 )
Change subject: x86: Add a fake SoC along with a board for build testing ......................................................................
Patch Set 1:
I don't see MAINBOARD_FAKE_X86 in the jenkins output as a board that was built though. Am I missing something?
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45710 )
Change subject: x86: Add a fake SoC along with a board for build testing ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45710/1/src/soc/fake/x86/chip.c File src/soc/fake/x86/chip.c:
https://review.coreboot.org/c/coreboot/+/45710/1/src/soc/fake/x86/chip.c@1 PS1, Line 1: #include <device/device.h> SPDX-License ?
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45710 )
Change subject: x86: Add a fake SoC along with a board for build testing ......................................................................
Patch Set 1:
I don't see MAINBOARD_FAKE_X86 in the jenkins output as a board that was built though. Am I missing something?
Thanks for spotting. Don't know yet what went wrong.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45710
to look at the new patch set (#2).
Change subject: x86: Add a fake SoC along with a board for build testing ......................................................................
x86: Add a fake SoC along with a board for build testing
This fake SoC code should serve as a minimal example how a buildable code base can look like.
Starting with a buildable commit should help with the review of the actual code, and also avoid any regressions when common coreboot code changes.
As the fake code itself is build-tested, it should advance with coreboot and can't rot like documentation might.
Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112 Signed-off-by: Nico Huber nico.h@gmx.de --- A src/mainboard/fake/Kconfig A src/mainboard/fake/Kconfig.name A src/mainboard/fake/x86/Kconfig A src/mainboard/fake/x86/Kconfig.name A src/mainboard/fake/x86/board_info.txt A src/mainboard/fake/x86/devicetree.cb A src/soc/fake/Kconfig A src/soc/fake/x86/Kconfig A src/soc/fake/x86/Makefile.inc A src/soc/fake/x86/cache_as_ram.S A src/soc/fake/x86/chip.c A src/soc/fake/x86/exit_car.S A src/soc/fake/x86/romstage.c A src/soc/fake/x86/timer.c 14 files changed, 126 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45710/2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45710 )
Change subject: x86: Add a fake SoC along with a board for build testing ......................................................................
Patch Set 1:
I don't see MAINBOARD_FAKE_X86 in the jenkins output as a board that was built though. Am I missing something?
Thanks for spotting. Don't know yet what went wrong.
Looks like abuild makes easy to miss assumptions :-/
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45710 )
Change subject: x86: Add a fake SoC along with a board for build testing ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45710/1/src/soc/fake/x86/chip.c File src/soc/fake/x86/chip.c:
https://review.coreboot.org/c/coreboot/+/45710/1/src/soc/fake/x86/chip.c@1 PS1, Line 1: #include <device/device.h>
SPDX-License ?
For what exactly? I wrote this from scratch and it contains not a single line of code. If I did something wrong, some lint script should have caught me.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45710 )
Change subject: x86: Add a fake SoC along with a board for build testing ......................................................................
Patch Set 2:
Patch Set 1:
I don't see MAINBOARD_FAKE_X86 in the jenkins output as a board that was built though. Am I missing something?
Thanks for spotting. Don't know yet what went wrong.
Looks like abuild makes easy to miss assumptions :-/
oh i see, BOARD vs MAINBOARD...
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45710 )
Change subject: x86: Add a fake SoC along with a board for build testing ......................................................................
Patch Set 2:
I don't see MAINBOARD_FAKE_X86 in the jenkins output as a board that was built though. Am I missing something?
Thanks for spotting. Don't know yet what went wrong.
Looks like abuild makes easy to miss assumptions :-/
oh i see, BOARD vs MAINBOARD...
Yeah, I suppose that's what one gets for not starting with a copy ;)
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45710
to look at the new patch set (#3).
Change subject: x86: Add a minimal example SoC along with a board ......................................................................
x86: Add a minimal example SoC along with a board
The min86 example SoC code along with the example mainboard should serve as a minimal example how a buildable x86 SoC code base can look like.
This can serve, for instance, as a basis to add new SoCs to coreboot. Starting with a buildable commit should help with the review of the actual code, and also avoid any regressions when common coreboot code changes.
As the example code itself is build-tested, it should advance with coreboot and can't rot like documentation might. It also serves as a check what APIs need to be implemented with the default Kconfig settings.
Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112 Signed-off-by: Nico Huber nico.h@gmx.de --- A src/mainboard/example/Kconfig A src/mainboard/example/Kconfig.name A src/mainboard/example/min86/Kconfig A src/mainboard/example/min86/Kconfig.name A src/mainboard/example/min86/board_info.txt A src/mainboard/example/min86/devicetree.cb A src/soc/example/Kconfig A src/soc/example/min86/Kconfig A src/soc/example/min86/Makefile.inc A src/soc/example/min86/cache_as_ram.S A src/soc/example/min86/chip.c A src/soc/example/min86/exit_car.S A src/soc/example/min86/romstage.c A src/soc/example/min86/timer.c 14 files changed, 126 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45710/3
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45710 )
Change subject: x86: Add a minimal example SoC along with a board ......................................................................
Patch Set 4: Code-Review+1
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45710 )
Change subject: x86: Add a minimal example SoC along with a board ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45710/1/src/soc/fake/x86/chip.c File src/soc/fake/x86/chip.c:
https://review.coreboot.org/c/coreboot/+/45710/1/src/soc/fake/x86/chip.c@1 PS1, Line 1: #include <device/device.h>
For what exactly? I wrote this from scratch and it contains not a single […]
Done, I guess
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45710 )
Change subject: x86: Add a minimal example SoC along with a board ......................................................................
Patch Set 4: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45710 )
Change subject: x86: Add a minimal example SoC along with a board ......................................................................
Patch Set 4:
I only understood that Nico wants this in just now.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45710 )
Change subject: x86: Add a minimal example SoC along with a board ......................................................................
Patch Set 5:
It still builds. I guess that was the point, so I'm going to submit it without giving it another look...
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45710 )
Change subject: x86: Add a minimal example SoC along with a board ......................................................................
x86: Add a minimal example SoC along with a board
The min86 example SoC code along with the example mainboard should serve as a minimal example how a buildable x86 SoC code base can look like.
This can serve, for instance, as a basis to add new SoCs to coreboot. Starting with a buildable commit should help with the review of the actual code, and also avoid any regressions when common coreboot code changes.
As the example code itself is build-tested, it should advance with coreboot and can't rot like documentation might. It also serves as a check what APIs need to be implemented with the default Kconfig settings.
Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112 Signed-off-by: Nico Huber nico.h@gmx.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/45710 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/mainboard/example/Kconfig A src/mainboard/example/Kconfig.name A src/mainboard/example/min86/Kconfig A src/mainboard/example/min86/Kconfig.name A src/mainboard/example/min86/board_info.txt A src/mainboard/example/min86/devicetree.cb A src/soc/example/Kconfig A src/soc/example/min86/Kconfig A src/soc/example/min86/Makefile.inc A src/soc/example/min86/cache_as_ram.S A src/soc/example/min86/chip.c A src/soc/example/min86/exit_car.S A src/soc/example/min86/romstage.c A src/soc/example/min86/timer.c 14 files changed, 126 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve
diff --git a/src/mainboard/example/Kconfig b/src/mainboard/example/Kconfig new file mode 100644 index 0000000..5afc8ee --- /dev/null +++ b/src/mainboard/example/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_EXAMPLE + +choice + prompt "Mainboard model" + +source "src/mainboard/example/*/Kconfig.name" + +endchoice + +source "src/mainboard/example/*/Kconfig" + +config MAINBOARD_VENDOR + default "Example" + +endif # VENDOR_EXAMPLE diff --git a/src/mainboard/example/Kconfig.name b/src/mainboard/example/Kconfig.name new file mode 100644 index 0000000..9ffc173 --- /dev/null +++ b/src/mainboard/example/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_EXAMPLE + bool "Example boards" diff --git a/src/mainboard/example/min86/Kconfig b/src/mainboard/example/min86/Kconfig new file mode 100644 index 0000000..3a962e2 --- /dev/null +++ b/src/mainboard/example/min86/Kconfig @@ -0,0 +1,14 @@ +if BOARD_EXAMPLE_MIN86 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_EXAMPLE_MIN86 + select MISSING_BOARD_RESET + +config MAINBOARD_DIR + default "example/min86" + +config MAINBOARD_PART_NUMBER + default "Min86" + +endif diff --git a/src/mainboard/example/min86/Kconfig.name b/src/mainboard/example/min86/Kconfig.name new file mode 100644 index 0000000..3313193 --- /dev/null +++ b/src/mainboard/example/min86/Kconfig.name @@ -0,0 +1,11 @@ +config BOARD_EXAMPLE_MIN86 + bool "Minimal x86 fake board" + help + This example mainboard code along with the example/min86 SoC + should serve as a minimal example how a buildable x86 SoC code + base can look like. + + This can serve, for instance, as a basis to add new SoCs to + coreboot. Starting with a buildable commit should help with + the review of the actual code, and also avoid any regressions + when common coreboot code changes. diff --git a/src/mainboard/example/min86/board_info.txt b/src/mainboard/example/min86/board_info.txt new file mode 100644 index 0000000..c778859 --- /dev/null +++ b/src/mainboard/example/min86/board_info.txt @@ -0,0 +1 @@ +Category: misc diff --git a/src/mainboard/example/min86/devicetree.cb b/src/mainboard/example/min86/devicetree.cb new file mode 100644 index 0000000..9af04c0 --- /dev/null +++ b/src/mainboard/example/min86/devicetree.cb @@ -0,0 +1,6 @@ +chip soc/example/min86 + + device domain 0 on + end + +end diff --git a/src/soc/example/Kconfig b/src/soc/example/Kconfig new file mode 100644 index 0000000..5bc004a --- /dev/null +++ b/src/soc/example/Kconfig @@ -0,0 +1 @@ +source "src/soc/example/*/Kconfig" diff --git a/src/soc/example/min86/Kconfig b/src/soc/example/min86/Kconfig new file mode 100644 index 0000000..38b23c0 --- /dev/null +++ b/src/soc/example/min86/Kconfig @@ -0,0 +1,25 @@ +config SOC_EXAMPLE_MIN86 + bool + help + This example SoC code along with the example/min86 mainboard + should serve as a minimal example how a buildable x86 SoC code + base can look like. + + This can serve, for instance, as a basis to add new SoCs to + coreboot. Starting with a buildable commit should help with + the review of the actual code, and also avoid any regressions + when common coreboot code changes. + +if SOC_EXAMPLE_MIN86 + +config SOC_SPECIFIC_OPTIONS + def_bool y + select ARCH_ALL_STAGES_X86_32 + select NO_MONOTONIC_TIMER + select NO_MMCONF_SUPPORT + select UNKNOWN_TSC_RATE + +config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld + default 0x100 + +endif diff --git a/src/soc/example/min86/Makefile.inc b/src/soc/example/min86/Makefile.inc new file mode 100644 index 0000000..9c1c7f0 --- /dev/null +++ b/src/soc/example/min86/Makefile.inc @@ -0,0 +1,15 @@ +ifeq ($(CONFIG_SOC_EXAMPLE_MIN86),y) + +bootblock-y += cache_as_ram.S +bootblock-y += ../../../cpu/intel/car/bootblock.c + +postcar-y += exit_car.S + +romstage-y += romstage.c + +ramstage-y += chip.c +ramstage-y += timer.c + +subdirs-y += ../../../cpu/x86/mtrr + +endif diff --git a/src/soc/example/min86/cache_as_ram.S b/src/soc/example/min86/cache_as_ram.S new file mode 100644 index 0000000..a350143 --- /dev/null +++ b/src/soc/example/min86/cache_as_ram.S @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.global bootblock_pre_c_entry + +.code32 +bootblock_pre_c_entry: + call bootblock_c_entry_bist + +.Lhlt: + hlt + jmp .Lhlt diff --git a/src/soc/example/min86/chip.c b/src/soc/example/min86/chip.c new file mode 100644 index 0000000..dd09891 --- /dev/null +++ b/src/soc/example/min86/chip.c @@ -0,0 +1,3 @@ +#include <device/device.h> + +struct chip_operations soc_example_min86_ops = { NULL }; diff --git a/src/soc/example/min86/exit_car.S b/src/soc/example/min86/exit_car.S new file mode 100644 index 0000000..0f1b227 --- /dev/null +++ b/src/soc/example/min86/exit_car.S @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.global chipset_teardown_car + +.code32 +chipset_teardown_car: + /* Return to caller. */ + jmp *%esp diff --git a/src/soc/example/min86/romstage.c b/src/soc/example/min86/romstage.c new file mode 100644 index 0000000..91074b2 --- /dev/null +++ b/src/soc/example/min86/romstage.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/cpu.h> + +asmlinkage void car_stage_entry(void) +{ +} diff --git a/src/soc/example/min86/timer.c b/src/soc/example/min86/timer.c new file mode 100644 index 0000000..9054ffd --- /dev/null +++ b/src/soc/example/min86/timer.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> + +void init_timer(void) +{ +}
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
-
Nico Huber (Code Review)
-
Tim Wawrzynczak (Code Review)