[S] Change in coreboot[master]: mb/google/nissa/var/uldren: Update DPTF parameters and tcc_offset

[Eric Lai (Code Review)]

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76105?usp=email )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/google/nissa/var/uldren: Update DPTF parameters and tcc_offset
......................................................................

mb/google/nissa/var/uldren: Update DPTF parameters and tcc_offset

Follow the Project_Uldren_Thermal_paramters_list_2023_0626.xlsx to
modify DPTF parameters and tcc_offset.
- Set tcc_offset to 3.
- Update Critical Policy trip point.
- Update Power Limits PL1 minimum step size to control limits (in mW).

BUG=b:282598257
BRANCH=firmware-nissa-15217.B
TEST=boot uldren to ChromeOS and pass thermal test.

Change-Id: Ic5bbb3aa3b036a1eae8a95f63b570db2dc6da978
Signed-off-by: Dtrain Hsu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76105
Reviewed-by: Sumeet R Pawnikar 
Reviewed-by: Eric Lai 
Tested-by: build bot (Jenkins) 
Reviewed-by: Paul Yang 
Reviewed-by: Ivan Chen 
Reviewed-by: Derek Huang 
---
M src/mainboard/google/brya/variants/uldren/overridetree.cb
1 file changed, 7 insertions(+), 5 deletions(-)

Approvals:
  Ivan Chen: Looks good to me, but someone else must approve
  Derek Huang: Looks good to me, but someone else must approve
  Sumeet R Pawnikar: Looks good to me, approved
  build bot (Jenkins): Verified
  Paul Yang: Looks good to me, but someone else must approve
  Eric Lai: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/uldren/overridetree.cb b/src/mainboard/google/brya/variants/uldren/overridetree.cb
index a873a62..973a6de 100644
--- a/src/mainboard/google/brya/variants/uldren/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldren/overridetree.cb
@@ -106,6 +106,8 @@
    	.vnn_icc_max_ma = 500,
    }"

+	register "tcc_offset" = "3"
+
    # Intel Common SoC Config
    #+-------------------+---------------------------+
    #| Field             |  Value                    |
@@ -175,10 +177,10 @@
    			}"
    			## Critical Policy
    			register "policies.critical" = "{
-					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
-					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      98, SHUTDOWN),
-					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      98, SHUTDOWN),
-					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      98, SHUTDOWN),
+					[0] = DPTF_CRITICAL(CPU,               130, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,     105, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,     105, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,     105, SHUTDOWN),
    			}"

register "controls.power_limits" = "{
@@ -187,7 +189,7 @@
    					.max_power = 6000,
    					.time_window_min = 28 * MSECS_PER_SEC,
    					.time_window_max = 28 * MSECS_PER_SEC,
-						.granularity = 250
+						.granularity = 125
    				},
    				.pl2 = {
    					.min_power = 25000,