[M] Change in coreboot[master]: soc/common/smbus: Add support for reading spd data via smbus for DDR5

[Tim Crawford (Code Review)]

Attention is currently required from: Angel Pons, Balaji Manigandan, Kapil Porwal, Karthik Ramasubramanian, Maulik Vaghela, Meera Ravindranath, Nick Vaccaro, Patrick Rudolph, Raj Astekar, Reka Norman, Subrata Banik, Tarun Tuli, Tim Wawrzynczak.

Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52731?usp=email )

Change subject: soc/common/smbus: Add support for reading spd data via smbus for DDR5
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Patch Set 14:

(1 comment)

File src/soc/intel/common/block/smbus/smbuslib.c:

https://review.coreboot.org/c/coreboot/+/52731/comment/2a73ba07_f41fa4e2 :
PS13, Line 10: {   0,               1 }, /* General Configuration section */
             : {   2,               2 }, /* General Configuration section */
             : {   3,              47 }, /* General Configuration section */
> This range looks contiguous to me, does the following not work? […]

If this code is correct, then these are not contiguous. In fact, the second line doesn't do anything.

{   2,               2 }, /* General Configuration section */