Change in coreboot[master]: soc/intel/{cnl, icl}: Make CONFIG_CPU_ADDR_BITS correct

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: soc/intel/{cnl, icl}: Make CONFIG_CPU_ADDR_BITS correct
......................................................................

soc/intel/{cnl, icl}: Make CONFIG_CPU_ADDR_BITS correct

This patch makes correct address bit value for CONFIG_CPU_ADDR_BITS.
> cat /proc/cpuinfo

address sizes	: 39 bits physical, 48 bits virtual

Also this change helps to generate correct MTRR mask value while
using set_var_mtrr().

Change-Id: Ie3185dd8d4af73ec0605e19e9aa4223f2c2ad462
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/icelake/Kconfig
2 files changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/34753/1

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 6dbf35f..d23cdf9 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -111,6 +111,10 @@
    select FSP_T_XIP if FSP_CAR
    select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE

+config CPU_ADDR_BITS
+	int
+	default 39
+
 config DCACHE_RAM_BASE
    default 0xfef00000

diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 99000bb..de2b4e7 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -62,6 +62,10 @@
    select DISPLAY_FSP_VERSION_INFO
    select HECI_DISABLE_USING_SMM

+config CPU_ADDR_BITS
+	int
+	default 39
+
 config DCACHE_RAM_BASE
    default 0xfef00000

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: soc/intel/{cnl, icl}: Make CONFIG_CPU_ADDR_BITS correct
......................................................................

Patch Set 1: Code-Review+1

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: soc/intel/{cnl, icl}: Make CONFIG_CPU_ADDR_BITS correct
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34753/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34753/1//COMMIT_MSG@7 
PS1, Line 7: soc/intel/{cnl, icl}: Make CONFIG_CPU_ADDR_BITS correct
Maybe:
> Correct CONFIG_CPU_ADDR_BITS

or
> Set CONFIG_CPU_ADDR_BITS to 39

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: soc/intel/{cnl, icl}: Make CONFIG_CPU_ADDR_BITS correct
......................................................................

Patch Set 1:

AFAICS this variable is deprecated and we trying to replace the remaining cases with cpu_phys_address_size() calls.

Change in coreboot[master]: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39

[Subrata Banik (Code Review)]

Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34753

to look at the new patch set (#2).

Change subject: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39
......................................................................

soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39

This patch makes correct address bit value for CONFIG_CPU_ADDR_BITS.
> cat /proc/cpuinfo

address sizes	: 39 bits physical, 48 bits virtual

Also this change helps to generate correct MTRR mask value while
using set_var_mtrr().

example:
set_var_mtrr(1, 0x99000000, 16*MiB, WP)

without CL:
0x0000000099000005: PHYBASE2: Address = 0x0000000099000000, WP
0x0000000fff000800: PHYMASK2: Length  = 0x0000007001000000, Valid

with CL:
0x0000000099000005: PHYBASE1: Address = 0x0000000099000000, WP
0x0000007fff000800: PHYMASK1: Length  = 0x0000000001000000, Valid

Change-Id: Ie3185dd8d4af73ec0605e19e9aa4223f2c2ad462
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/icelake/Kconfig
2 files changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/34753/2

Change in coreboot[master]: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34753/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34753/1//COMMIT_MSG@7 
PS1, Line 7: soc/intel/{cnl, icl}: Make CONFIG_CPU_ADDR_BITS correct
> Maybe: […]

Done

Change in coreboot[master]: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39

[Subrata Banik (Code Review)]

Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34753

to look at the new patch set (#3).

Change subject: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39
......................................................................

soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39

This patch makes correct address bit value for CONFIG_CPU_ADDR_BITS.
> cat /proc/cpuinfo

address sizes	: 39 bits physical, 48 bits virtual

Also this change helps to generate correct MTRR mask value while
using set_var_mtrr().

example:
set_var_mtrr(1, 0x99000000, 16*MiB, WP)

without CL :
0x0000000099000005: PHYBASE2: Address = 0x0000000099000000, WP
0x0000000fff000800: PHYMASK2: Length  = 0x0000007001000000, Valid

with CL :
0x0000000099000005: PHYBASE1: Address = 0x0000000099000000, WP
0x0000007fff000800: PHYMASK1: Length  = 0x0000000001000000, Valid

Change-Id: Ie3185dd8d4af73ec0605e19e9aa4223f2c2ad462
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/icelake/Kconfig
2 files changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/34753/3

Change in coreboot[master]: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39
......................................................................

Patch Set 3: Code-Review+1

Change in coreboot[master]: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39
......................................................................

Patch Set 3: Code-Review+2

Change in coreboot[master]: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39

[Furquan Shaikh (Code Review)]

Furquan Shaikh has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39
......................................................................

Removed Code-Review+2 by Furquan Shaikh

Change in coreboot[master]: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34753/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34753/3//COMMIT_MSG@14 
PS3, Line 14: Also this change helps to generate correct MTRR mask value while
            : using set_var_mtrr
Is this a problem only in bootblock? i.e. with early MTRR?

Change in coreboot[master]: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34753/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34753/3//COMMIT_MSG@14 
PS3, Line 14: Also this change helps to generate correct MTRR mask value while
            : using set_var_mtrr
> Is this a problem only in bootblock? i.e. […]

till romstage.

Change in coreboot[master]: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34753/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34753/3//COMMIT_MSG@14 
PS3, Line 14: Also this change helps to generate correct MTRR mask value while
            : using set_var_mtrr
> till romstage.

Is the problem fixed by using cpu_phys_address_size() in earlymtrr.c?

Change in coreboot[master]: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34753/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34753/3//COMMIT_MSG@14 
PS3, Line 14: Also this change helps to generate correct MTRR mask value while
            : using set_var_mtrr
> Is the problem fixed by using cpu_phys_address_size() in earlymtrr. […]

should be yes, i was actually using set_var_mtrr as many places in common code block we are using set_var_mtrr  for enabling temp MTRR.

As per my understating all set_var_mtrr() usage might need this change to make it proper or else lets replace CONFIG_CPU_ADDR_BITS in set_var_mtrr() with  cpu_phys_address_size() to fix for all.

Change in coreboot[master]: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34753/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34753/3//COMMIT_MSG@14 
PS3, Line 14: Also this change helps to generate correct MTRR mask value while
            : using set_var_mtrr
> should be yes, i was actually using set_var_mtrr as many places in common code block we are using se […]

I was referring to basically something like this:

diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 02ad85f321..5d7ff2cf45 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -11,6 +11,7 @@
  * GNU General Public License for more details.
  */

+#include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
@@ -51,6 +52,6 @@ void set_var_mtrr(
        basem.hi = 0;
        wrmsr(MTRR_PHYS_BASE(reg), basem);
        maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
-       maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
+       maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1;
        wrmsr(MTRR_PHYS_MASK(reg), maskm);
 }

Change in coreboot[master]: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: soc/intel/{cnl, icl}: Set CONFIG_CPU_ADDR_BITS to 39
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34753/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34753/3//COMMIT_MSG@14 
PS3, Line 14: Also this change helps to generate correct MTRR mask value while
            : using set_var_mtrr
> I was referring to basically something like this: […]

:) yes, on it

Change in coreboot[master]: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()

[Subrata Banik (Code Review)]

Hello Aaron Durbin, Patrick Rudolph, Aamir Bohra, Duncan Laurie, Paul Menzel, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34753

to look at the new patch set (#4).

Change subject: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()
......................................................................

cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()

This patch helps to generate correct MTRR mask value while
using set_var_mtrr().

example:
set_var_mtrr(1, 0x99000000, 16*MiB, WP)

without CL :
0x0000000099000005: PHYBASE2: Address = 0x0000000099000000, WP
0x0000000fff000800: PHYMASK2: Length  = 0x0000007001000000, Valid

with CL :
0x0000000099000005: PHYBASE1: Address = 0x0000000099000000, WP
0x0000007fff000800: PHYMASK1: Length  = 0x0000000001000000, Valid

Change-Id: Ie3185dd8d4af73ec0605e19e9aa4223f2c2ad462
Signed-off-by: Subrata Banik 
---
M src/cpu/x86/mtrr/earlymtrr.c
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/34753/4

Change in coreboot[master]: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()
......................................................................

Patch Set 4: Code-Review+2

As a follow up, I believe we can get rid of CPU_ADDR_BITS from Kconfig for apollolake and skylake now?

Change in coreboot[master]: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()
......................................................................

Patch Set 4:
> Patch Set 4: Code-Review+2
>
> As a follow up, I believe we can get rid of CPU_ADDR_BITS from Kconfig for apollolake and skylake now?

totally agree, then those Kconfig are stale now

Change in coreboot[master]: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34753/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34753/3//COMMIT_MSG@14 
PS3, Line 14: Also this change helps to generate correct MTRR mask value while
            : using set_var_mtrr
> :) yes, on it

Ack

Change in coreboot[master]: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()

[Subrata Banik (Code Review)]

Hello Aaron Durbin, Patrick Rudolph, Aamir Bohra, Duncan Laurie, Paul Menzel, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34753

to look at the new patch set (#5).

Change subject: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()
......................................................................

cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()

This patch helps to generate correct MTRR mask value while
using set_var_mtrr().

example:
set_var_mtrr(1, 0x99000000, 16*MiB, WP)

without CL :
0x0000000099000005: PHYBASE2: Address = 0x0000000099000000, WP
0x0000000fff000800: PHYMASK2: Length  = 0x0000007001000000, Valid

with CL :
0x0000000099000005: PHYBASE1: Address = 0x0000000099000000, WP
0x0000007fff000800: PHYMASK1: Length  = 0x0000000001000000, Valid

Change-Id: Ie3185dd8d4af73ec0605e19e9aa4223f2c2ad462
Signed-off-by: Subrata Banik 
---
M src/cpu/x86/mtrr/earlymtrr.c
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/34753/5

Change in coreboot[master]: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()
......................................................................

Patch Set 4:

LGTM, just that I would try another approach than calling set_var_mtrr() in general for the postcar-skipping approach. This change also affects older AMD cpus.

I am pretty sure some of those had errata on the cpuid() commands that get added but I could not find a reference now.

Change in coreboot[master]: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()
......................................................................

Patch Set 5:
> Patch Set 4:
>
> just that I would try another approach than calling set_var_mtrr() in general for the postcar-skipping approach.

yes, that would be different problem to solve

Change in coreboot[master]: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()

[V Sowmya (Code Review)]

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()
......................................................................

Patch Set 5: Code-Review+2

Change in coreboot[master]: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34753 )

Change subject: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()
......................................................................

cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()

This patch helps to generate correct MTRR mask value while
using set_var_mtrr().

example:
set_var_mtrr(1, 0x99000000, 16*MiB, WP)

without CL :
0x0000000099000005: PHYBASE2: Address = 0x0000000099000000, WP
0x0000000fff000800: PHYMASK2: Length  = 0x0000007001000000, Valid

with CL :
0x0000000099000005: PHYBASE1: Address = 0x0000000099000000, WP
0x0000007fff000800: PHYMASK1: Length  = 0x0000000001000000, Valid

Change-Id: Ie3185dd8d4af73ec0605e19e9aa4223f2c2ad462
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34753
Reviewed-by: V Sowmya 
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/cpu/x86/mtrr/earlymtrr.c
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  V Sowmya: Looks good to me, approved

diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 02ad85f..5d7ff2c 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -11,6 +11,7 @@
  * GNU General Public License for more details.
  */

+#include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
@@ -51,6 +52,6 @@
    basem.hi = 0;
    wrmsr(MTRR_PHYS_BASE(reg), basem);
    maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
-	maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
+	maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1;
    wrmsr(MTRR_PHYS_MASK(reg), maskm);
 }