[XS] Change in coreboot[master]: soc/intel/alderlake/meminit.c: Guard CsPiStartHighinEct properly

[Michał Żygowski (Code Review)]

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76915?usp=email )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/alderlake/meminit.c: Guard CsPiStartHighinEct properly
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soc/intel/alderlake/meminit.c: Guard CsPiStartHighinEct properly

Build issue introduced by patch CB:76418 (commit hash
01025d3ae78e02192d389f22abd36747e3d8c63b) for Google boards.
Patch has not been rebased to latest master and tested before
submission causing the Jenkins jobs to fail.

Change-Id: I95bd2485b98be4ab3a39eaaebb9efb34db93bbe8
Signed-off-by: Michał Żygowski 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76915
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/alderlake/meminit.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index 42b6698..35c3252 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -240,7 +240,7 @@
    bool dq_dqs_auto_detect = false;
    FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;

-#if CONFIG(SOC_INTEL_RAPTORLAKE)
+#if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO)
    mem_cfg->CsPiStartHighinEct = mb_cfg->cs_pi_start_high_in_ect;
 #endif
    mem_cfg->ECT = mb_cfg->ect;