[S] Change in coreboot[main]: sb/intel/i82801gx/lpc.c: Refactor i82801gx_gpi_routing()

[Elyes Haouas (Code Review)]

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83492?usp=email )

Change subject: sb/intel/i82801gx/lpc.c: Refactor i82801gx_gpi_routing()
......................................................................

sb/intel/i82801gx/lpc.c: Refactor i82801gx_gpi_routing()

Change-Id: Ie6ad4d481d9e1194ca971710cce55e8fc639f826
Signed-off-by: Elyes Haouas 
---
M src/southbridge/intel/i82801gx/lpc.c
1 file changed, 8 insertions(+), 17 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/83492/1

diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index a04b4b9..48b2573 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -115,24 +115,15 @@
    /* Get the chip configuration */
    const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
    u32 reg32 = 0;
+	int i;
+	uint8_t gpi_routing[] = {config->gpi0_routing, config->gpi1_routing, config->gpi2_routing,
+		config->gpi3_routing, config->gpi4_routing, config->gpi5_routing, config->gpi6_routing,
+		config->gpi7_routing, config->gpi8_routing, config->gpi9_routing, config->gpi10_routing,
+		config->gpi11_routing, config->gpi12_routing, config->gpi13_routing, config->gpi14_routing,
+		config->gpi15_routing};

-	/* An array would be much nicer here, or some other method of doing this. */
-	reg32 |= (config->gpi0_routing & 0x03) << 0;
-	reg32 |= (config->gpi1_routing & 0x03) << 2;
-	reg32 |= (config->gpi2_routing & 0x03) << 4;
-	reg32 |= (config->gpi3_routing & 0x03) << 6;
-	reg32 |= (config->gpi4_routing & 0x03) << 8;
-	reg32 |= (config->gpi5_routing & 0x03) << 10;
-	reg32 |= (config->gpi6_routing & 0x03) << 12;
-	reg32 |= (config->gpi7_routing & 0x03) << 14;
-	reg32 |= (config->gpi8_routing & 0x03) << 16;
-	reg32 |= (config->gpi9_routing & 0x03) << 18;
-	reg32 |= (config->gpi10_routing & 0x03) << 20;
-	reg32 |= (config->gpi11_routing & 0x03) << 22;
-	reg32 |= (config->gpi12_routing & 0x03) << 24;
-	reg32 |= (config->gpi13_routing & 0x03) << 26;
-	reg32 |= (config->gpi14_routing & 0x03) << 28;
-	reg32 |= (config->gpi15_routing & 0x03) << 30;
+	for (i = 0; i < sizeof(gpi_routing) / sizeof(gpi_routing[0]); i++)
+		reg32 |= (gpi_routing[i] & 0x03) << (i * 2);

pci_write_config32(dev, GPIO_ROUT, reg32);
 }