Attention is currently required from: Tim Crawford, Jeremy Soller, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56949 )
Change subject: soc/intel/tigerlake: Add TGL-H PEG ports ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/56949/comment/6e2270b7_cf6ada3f PS2, Line 195: if (is_devfn_enabled(SA_DEVFN_CPU_PCIE)) { : m_cfg->CpuPcieRpEnableMask |= (1 << 0); : } : if (is_devfn_enabled(SA_DEVFN_PEG1)) { : m_cfg->CpuPcieRpEnableMask |= (1 << 1); : } : if (is_devfn_enabled(SA_DEVFN_PEG2)) { : m_cfg->CpuPcieRpEnableMask |= (1 << 2); : } : if (is_devfn_enabled(SA_DEVFN_PEG3)) { : m_cfg->CpuPcieRpEnableMask |= (1 << 3); : } WDYT about? ``` const unsigned int cpu_pcie_devs[] = { SA_DEVFN_CPU_CPIE, SA_DEVFN_PEG1, ... }; for (unsigned int i = 0; i < ARRAY_SIZE(cpu_pcie_devs); i++) if (is_devfn_enabled(cpu_pcie_devs[i])) m_cfg->CpuPcieRpEnableMask |= 1 << i; ```