Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42660 )
Change subject: sb/intel/common: Add early SPI code ......................................................................
sb/intel/common: Add early SPI code
All Intel southbridges with SPI perform this write. Put it inside a function in common code. Use a different name to avoid a name clash.
Change-Id: I3c284d6cffd22949d50b4c4f9846ceaef38d7cda Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/early_spi.c A src/southbridge/intel/common/early_spi.h 3 files changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/42660/1
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index b3c48fa..3ebc5fb 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -24,6 +24,8 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
+bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += early_spi.c + all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c ifeq ($(CONFIG_SPI_FLASH_SMM),y) smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c diff --git a/src/southbridge/intel/common/early_spi.c b/src/southbridge/intel/common/early_spi.c new file mode 100644 index 0000000..77e2309 --- /dev/null +++ b/src/southbridge/intel/common/early_spi.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <southbridge/intel/common/early_spi.h> + +void enable_spi_prefetching_and_caching(void) +{ + pci_update_config8(PCI_DEV(0, 0x1f, 0), BIOS_CNTL, ~(3 << 2), 2 << 2); +} diff --git a/src/southbridge/intel/common/early_spi.h b/src/southbridge/intel/common/early_spi.h new file mode 100644 index 0000000..618cc9d --- /dev/null +++ b/src/southbridge/intel/common/early_spi.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_EARLY_SPI_H +#define SOUTHBRIDGE_INTEL_COMMON_EARLY_SPI_H + +#define BIOS_CNTL 0xDC + +void enable_spi_prefetching_and_caching(void); + +#endif
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42660
to look at the new patch set (#3).
Change subject: sb/intel/common: Add early SPI code ......................................................................
sb/intel/common: Add early SPI code
All Intel southbridges with SPI perform this write. Put it inside a function in common code. Use a different name to avoid a name clash.
As it is only one statement, make it inline so that it can be defined on the header itself. It is only called once per southbridge anyway.
Change-Id: I3c284d6cffd22949d50b4c4f9846ceaef38d7cda Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/southbridge/intel/common/early_spi.h 1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/42660/3
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42660 )
Change subject: sb/intel/common: Add early SPI code ......................................................................
Patch Set 3: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42660 )
Change subject: sb/intel/common: Add early SPI code ......................................................................
sb/intel/common: Add early SPI code
All Intel southbridges with SPI perform this write. Put it inside a function in common code. Use a different name to avoid a name clash.
As it is only one statement, make it inline so that it can be defined on the header itself. It is only called once per southbridge anyway.
Change-Id: I3c284d6cffd22949d50b4c4f9846ceaef38d7cda Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42660 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- A src/southbridge/intel/common/early_spi.h 1 file changed, 13 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/southbridge/intel/common/early_spi.h b/src/southbridge/intel/common/early_spi.h new file mode 100644 index 0000000..ae84f74 --- /dev/null +++ b/src/southbridge/intel/common/early_spi.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_EARLY_SPI_H +#define SOUTHBRIDGE_INTEL_COMMON_EARLY_SPI_H + +#include <device/pci_ops.h> + +static inline void enable_spi_prefetching_and_caching(void) +{ + pci_update_config8(PCI_DEV(0, 0x1f, 0), 0xdc, ~(3 << 2), 2 << 2); +} + +#endif