Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43876 )
Change subject: mb/google/poppy/var/atlas: Relocate devicetree FSP settings ......................................................................
mb/google/poppy/var/atlas: Relocate devicetree FSP settings
Also drop some redundant comments about these settings.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I4f685a581933e539e43ec62229ab6d2eb099996c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb 1 file changed, 81 insertions(+), 89 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/43876/1
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index d54f716..a7b66bc 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -42,26 +42,12 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" - register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "1" - register "SaImguEnable" = "1" - register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "0" + register "IoBufferOwnership" = "3" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s @@ -149,14 +135,6 @@ .dc_loadline = 425, }"
- # PCIe Root port 1 with SRCCLKREQ1# (WLAN) - register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpClkSrcNumber[0]" = "1" - register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" - # USB 2.0 register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty @@ -171,68 +149,10 @@ register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
- # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C0 | Touchscreen | - #| I2C2 | Trackpad | - #| I2C3 | Camera | - #| I2C4 | Audio | - #| pch_thermal_trip | PCH Trip Temperature | - #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 98, - .fall_time_ns = 38, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 186, - .scl_hcnt = 93, - .sda_hold = 36, - }, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 98, - .fall_time_ns = 38, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 176, - .scl_hcnt = 95, - .sda_hold = 36, - } - }, - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, .pch_thermal_trip = 75, }" - # Touchscreen - register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" - - # Trackpad - register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" - - # Camera - register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" - - # Audio - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -254,6 +174,13 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + + # FIXME: corresponding device entry is missing + register "Device4Enable" = "1" + + # FIXME: corresponding device entry is missing + register "SaImguEnable" = "1" + device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on chip drivers/usb/acpi @@ -282,6 +209,12 @@ device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 15.0 on + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" + register "common_soc_config.i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 98, + .fall_time_ns = 38, + }" chip drivers/i2c/hid register "generic.hid" = ""ACPI0C50"" register "generic.desc" = ""STM Touchscreen"" @@ -302,6 +235,16 @@ end # I2C #0 - Touchscreen device pci 15.1 off end # I2C #1 device pci 15.2 on + register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" + register "common_soc_config.i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 186, + .scl_hcnt = 93, + .sda_hold = 36, + }, + }" chip drivers/i2c/hid register "generic.hid" = ""ACPI0C50"" register "generic.desc" = ""ELAN Touchpad"" @@ -311,16 +254,42 @@ device i2c 0x15 on end end end # I2C #2 - Trackpad - device pci 15.3 on end # I2C #3 - Camera - device pci 16.0 on end # Management Engine Interface 1 + device pci 15.3 on # I2C #3 - Camera + register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" + register "common_soc_config.i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 98, + .fall_time_ns = 38, + }" + end + device pci 16.0 on # Management Engine Interface 1 + + # FIXME: does not match devicetree! + register "HeciEnabled" = "0" + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 off end # SATA + device pci 17.0 off # SATA + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" + end device pci 19.0 on end # UART #2 device pci 19.1 off end # I2C #5 device pci 19.2 on + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" + register "common_soc_config.i2c[4]" = "{ + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 176, + .scl_hcnt = 95, + .sda_hold = 36, + } + }" chip drivers/i2c/max98373 register "vmon_slot_no" = "4" register "imon_slot_no" = "5" @@ -356,6 +325,12 @@ end end # I2C #4 - Audio device pci 1c.0 on + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpClkSrcNumber[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" chip drivers/intel/wifi register "wake" = "GPE0_DW1_07" # GPP_B7 device pci 00.0 on end @@ -375,6 +350,10 @@ device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 on + register "common_soc_config.gspi[0]" = "{ + .speed_mhz = 1, + .early_init = 1, + }" chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cr50"" @@ -383,9 +362,14 @@ end end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1e.4 on end # eMMC + device pci 1e.4 on # eMMC + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + end device pci 1e.5 off end # SDIO - device pci 1e.6 off end # SDCard + device pci 1e.6 off # SDCard + register "ScsSdCardEnabled" = "0" + end device pci 1f.0 on chip ec/google/chromeec device pnp 0c09.0 on end @@ -393,9 +377,17 @@ end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus + device pci 1f.3 on # Intel HDA + register "EnableAzalia" = "1" + end + device pci 1f.4 on # SMBus + register "SmbusEnable" = "1" + end device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device pci 1f.6 off # GbE + register "EnableLan" = "0" + end + + register "EnableTraceHub" = "0" end end
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43876
to look at the new patch set (#2).
Change subject: mb/google/poppy/var/atlas: Relocate devicetree FSP settings ......................................................................
mb/google/poppy/var/atlas: Relocate devicetree FSP settings
Also drop some redundant comments about these settings.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I4f685a581933e539e43ec62229ab6d2eb099996c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb 1 file changed, 80 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/43876/2
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43876
to look at the new patch set (#3).
Change subject: mb/google/poppy/var/atlas: Relocate devicetree settings ......................................................................
mb/google/poppy/var/atlas: Relocate devicetree settings
Also drop some redundant comments about these settings.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I4f685a581933e539e43ec62229ab6d2eb099996c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb 1 file changed, 80 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/43876/3
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43876 )
Change subject: mb/google/poppy/var/atlas: Relocate devicetree settings ......................................................................
Abandoned
-
Angel Pons (Code Review)