Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/35614 )
Change subject: [WIP] gma skl: Implement CDClk switching ......................................................................
[WIP] gma skl: Implement CDClk switching
Change-Id: Ic14cf5981540d36d3f337a43bbec3574be0d3c99 Signed-off-by: Nico Huber nico.h@gmx.de --- M common/hw-gfx-gma.adb M common/hw-gfx.ads M common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb M common/skylake/hw-gfx-gma-power_and_clocks_skylake.ads 4 files changed, 111 insertions(+), 52 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/14/35614/1
diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 462f5c4..5898ab2 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -292,6 +292,8 @@ (New_Configs (P).Framebuffer, New_Configs (P).Mode, P)); end loop;
+ Power_And_Clocks.Update_CDClk (New_Configs); + -- enable all pipes that changed and should be active for Pipe in Pipe_Index loop declare diff --git a/common/hw-gfx.ads b/common/hw-gfx.ads index 93a3684..9a4015c 100644 --- a/common/hw-gfx.ads +++ b/common/hw-gfx.ads @@ -66,7 +66,7 @@ Rotation => No_Rotation, Offset => 0);
- subtype Frequency_Type is Pos64 range 19_200_000 .. 624_000_000; + subtype Frequency_Type is Pos64 range 19_200_000 .. 675_000_000;
type DP_Lane_Count is (DP_Lane_Count_1, DP_Lane_Count_2, DP_Lane_Count_4); subtype DP_Lane_Count_Type is Pos64 range 1 .. 4; diff --git a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb index c6eb2cf..9383aef 100644 --- a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb +++ b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb @@ -17,6 +17,7 @@ with HW.Time; with HW.Debug; with HW.GFX.GMA.Config; +with HW.GFX.GMA.Config_Helpers; with HW.GFX.GMA.Registers; with HW.GFX.GMA.Power_And_Clocks_Haswell;
@@ -88,12 +89,10 @@
GT_MAILBOX_READY : constant := 1 * 2 ** 31;
- function CDCLK_CTL_CD_FREQ_DECIMAL - (Freq : Pos16; - Plus_Half : Boolean) - return Word32 is + function CDCLK_CTL_CD_FREQ_DECIMAL (CDClk : Frequency_Type) return Word32 is begin - return Word32 (2 * (Pos32 (Freq) - 1)) or (if Plus_Half then 1 else 0); + -- Weirdest representation: CDClk - 1MHz in 10.1 (10 + 1 fractional bit) + return Word32 ((CDClk - 1_000_000) / 500_000); end CDCLK_CTL_CD_FREQ_DECIMAL;
---------------------------------------------------------------------------- @@ -249,41 +248,36 @@ PD_Off (PW1); end Post_All_Off;
- procedure Initialize + function Normalize_CDClk (CDClk : in Int64) return Frequency_Type is + ( if CDClk > 540_000_000 then 675_000_000 + elsif CDClk > 450_000_000 then 540_000_000 + elsif CDClk > 337_500_000 then 450_000_000 + else 337_500_000); + + procedure Set_CDClk (CDClk : in out Frequency_Type) is - CDClk_Change_Timeout : Time.T; - Timed_Out : Boolean; + CDClk_Change_Timeout : constant Time.T := Time.MS_From_Now(3); + Timed_Out : Boolean := False;
MBox_Data0 : Word32; + + Want : constant Frequency_Type := Normalize_CDClk (CDClk); + CDCLK_CTL_CD_Freq : constant Word32 := + (case Want is + when 675_000_000 => CDCLK_CTL_CD_FREQ_SELECT_675MHZ, + when 540_000_000 => CDCLK_CTL_CD_FREQ_SELECT_540MHZ, + when 450_000_000 => CDCLK_CTL_CD_FREQ_SELECT_450MHZ, + when others => CDCLK_CTL_CD_FREQ_SELECT_337_5MHZ) or + CDCLK_CTL_CD_FREQ_DECIMAL (Want); + SKL_CDCLK_Voltage_Level : constant Word64 := + (case Want is + when 675_000_000 => 3, + when 540_000_000 => 2, + when 450_000_000 => 1, + when others => 0); + + CDCLK_CTL : Word32; begin - Registers.Set_Mask - (Register => Registers.NDE_RSTWRN_OPT, - Mask => NDE_RSTWRN_OPT_RST_PCH_Handshake_En); - - Registers.Wait_Set_Mask - (Register => Registers.FUSE_STATUS, - Mask => FUSE_STATUS_PG0_DIST_STATUS); - PD_On (PW1); - PD_On (MISC_IO); - - Registers.Write - (Register => Registers.CDCLK_CTL, - Value => CDCLK_CTL_CD_FREQ_SELECT_337_5MHZ or - CDCLK_CTL_CD_FREQ_DECIMAL (337, True)); - -- TODO: Set to preferred eDP rate: - -- Registers.Unset_And_Set_Mask - -- (Register => Registers.DPLL_CTRL1, - -- Unset_Mask => DPLL_CTRL1_DPLL0_LINK_RATE_MASK, - -- Set_Mask => DPLL_CTRL1_DPLL0_LINK_RATE_...); - Registers.Set_Mask - (Register => Registers.LCPLL1_CTL, - Mask => LCPLL1_CTL_PLL_ENABLE); - Registers.Wait_Set_Mask - (Register => Registers.LCPLL1_CTL, - Mask => LCPLL1_CTL_PLL_LOCK); - - CDClk_Change_Timeout := Time.MS_From_Now (3); - Timed_Out := False; loop GT_Mailbox_Write (MBox => SKL_PCODE_CDCLK_CONTROL, @@ -298,27 +292,79 @@
Timed_Out := Time.Timed_Out (CDClk_Change_Timeout); end loop; - pragma Debug (Timed_Out, Debug.Put_Line - ("ERROR: PCODE not ready for frequency change after 3ms."));
- if not Timed_Out then - GT_Mailbox_Write - (MBox => SKL_PCODE_CDCLK_CONTROL, - Value => 16#0000_0000#); -- 0 - 337.5MHz - -- 1 - 450.0MHz - -- 2 - 540.0MHz - -- 3 - 675.0MHz - Registers.Set_Mask - (Register => Registers.DBUF_CTL, - Mask => DBUF_CTL_DBUF_POWER_REQUEST); - Registers.Wait_Set_Mask - (Register => Registers.DBUF_CTL, - Mask => DBUF_CTL_DBUF_POWER_STATE); + if Timed_Out then + pragma Debug (Debug.Put_Line + ("ERROR: PCODE not ready for frequency change after 3ms.")); + Registers.Read(Registers.CDCLK_CTL, CDCLK_CTL); + CDCLK_CTL := CDCLK_CTL and CDCLK_CTL_CD_FREQ_DECIMAL_MASK; + CDClk := Normalize_CDClk (Int64 (CDCLK_CTL) * 500_000 + 1_000_000); + return; end if;
+ Registers.Write (Registers.CDCLK_CTL, CDCLK_CTL_CD_Freq); + CDClk := Want; + + GT_Mailbox_Write + (MBox => SKL_PCODE_CDCLK_CONTROL, + Value => SKL_CDCLK_Voltage_Level); + Registers.Set_Mask + (Register => Registers.DBUF_CTL, + Mask => DBUF_CTL_DBUF_POWER_REQUEST); + Registers.Wait_Set_Mask + (Register => Registers.DBUF_CTL, + Mask => DBUF_CTL_DBUF_POWER_STATE); + end Set_CDClk; + + procedure Initialize + is + Default_CDClk : Frequency_Type := 337_500_000; + begin + Registers.Set_Mask + (Register => Registers.NDE_RSTWRN_OPT, + Mask => NDE_RSTWRN_OPT_RST_PCH_Handshake_En); + + Registers.Wait_Set_Mask + (Register => Registers.FUSE_STATUS, + Mask => FUSE_STATUS_PG0_DIST_STATUS); + PD_On (PW1); + PD_On (MISC_IO); + + Registers.Write + (Register => Registers.CDCLK_CTL, + Value => CDCLK_CTL_CD_FREQ_SELECT_337_5MHZ or + CDCLK_CTL_CD_FREQ_DECIMAL (Default_CDClk)); + -- TODO: Set to preferred eDP rate: + -- Registers.Unset_And_Set_Mask + -- (Register => Registers.DPLL_CTRL1, + -- Unset_Mask => DPLL_CTRL1_DPLL0_LINK_RATE_MASK, + -- Set_Mask => DPLL_CTRL1_DPLL0_LINK_RATE_...); + Registers.Set_Mask + (Register => Registers.LCPLL1_CTL, + Mask => LCPLL1_CTL_PLL_ENABLE); + Registers.Wait_Set_Mask + (Register => Registers.LCPLL1_CTL, + Mask => LCPLL1_CTL_PLL_LOCK); + + pragma Warnings + (GNAT, Off, """Default_CDClk"" modified by call*", + Reason => "Can only be 337.5MHz here"); + pragma Warnings (GNATprove, Off, "*assignment to ""Default_CDClk"""); + Set_CDClk (Default_CDClk); + pragma Warnings (GNATprove, On, "*assignment to ""Default_CDClk"""); + pragma Warnings (GNAT, On, """Default_CDClk"" modified by call*"); + Config.Raw_Clock := Config.Default_RawClk_Freq; end Initialize;
+ procedure Update_CDClk (Configs : in out Pipe_Configs) + is + CDClk : Frequency_Type := Config_Helpers.Highest_Dotclock (Configs); + begin + Set_CDClk (CDClk); + Config_Helpers.Limit_Dotclock (Configs, CDClk); + end Update_CDClk; + procedure Power_Set_To (Configs : Pipe_Configs) is begin for PD in reverse Dynamic_Domain loop diff --git a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.ads b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.ads index 4db9ab5..75f2d2e 100644 --- a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.ads +++ b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.ads @@ -19,6 +19,17 @@
procedure Initialize;
+ procedure Update_CDClk (Configs : in out Pipe_Configs) + with + Post => + (for all P in Pipe_Index => + Configs (P).Port = Disabled or + (Configs (P).Port = Configs'Old (P).Port and + Configs (P).Framebuffer = Configs'Old (P).Framebuffer and + Configs (P).Cursor = Configs'Old (P).Cursor and + Configs (P).Mode.H_Visible = Configs'Old (P).Mode.H_Visible and + Configs (P).Mode.V_Visible = Configs'Old (P).Mode.V_Visible)); + procedure Power_Set_To (Configs : Pipe_Configs); procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs); procedure Power_Down (Old_Configs, Tmp_Configs, New_Configs : Pipe_Configs);
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/35614 )
Change subject: [WIP] gma skl: Implement CDClk switching ......................................................................
Patch Set 1: Code-Review+1
patch train tested on Librem 15v3 (1080p) and 15v4 (2048p), both functional with CDCLK set correctly
Hello Matt DeVillier,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/libgfxinit/+/35614
to look at the new patch set (#2).
Change subject: [WIP] gma skl: Implement CDClk switching ......................................................................
[WIP] gma skl: Implement CDClk switching
Change-Id: Ic14cf5981540d36d3f337a43bbec3574be0d3c99 Signed-off-by: Nico Huber nico.h@gmx.de --- M common/hw-gfx-gma-config_helpers.ads M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.adb M common/hw-gfx.ads M common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb M common/skylake/hw-gfx-gma-power_and_clocks_skylake.ads 6 files changed, 163 insertions(+), 52 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/14/35614/2
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/35614 )
Change subject: [WIP] gma skl: Implement CDClk switching ......................................................................
Patch Set 2: Code-Review+1
Hello Arthur Heymans, Matt DeVillier, Thomas Heijligen,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/libgfxinit/+/35614
to look at the new patch set (#3).
Change subject: gma skl: Implement CDClk switching ......................................................................
gma skl: Implement CDClk switching
Flow is roughly the same as for Broadwell. Maximum CDClk is now completely controlled by fuses, though. The same frequencies are supported and dot clocks can run at full CDClk speed.
Change-Id: Ic14cf5981540d36d3f337a43bbec3574be0d3c99 Signed-off-by: Nico Huber nico.h@gmx.de --- M common/hw-gfx-gma-registers.ads M common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb M common/skylake/hw-gfx-gma-power_and_clocks_skylake.ads 3 files changed, 117 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/14/35614/3
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/35614 )
Change subject: gma skl: Implement CDClk switching ......................................................................
Patch Set 4: Verified+1
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/35614 )
Change subject: gma skl: Implement CDClk switching ......................................................................
Patch Set 5: Verified+1
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/35614 )
Change subject: gma skl: Implement CDClk switching ......................................................................
Patch Set 6: Code-Review+1
tested on Purism Librem 15v4 w/4k display
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/35614 )
Change subject: gma skl: Implement CDClk switching ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/libgfxinit/+/35614/6/common/hw-gfx-gma-registe... File common/hw-gfx-gma-registers.ads:
https://review.coreboot.org/c/libgfxinit/+/35614/6/common/hw-gfx-gma-registe... PS6, Line 1464: DFSM => 16#05_1000# / Register_Width, Does order matter here? Looks like this offset should go a bit lower.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/35614 )
Change subject: gma skl: Implement CDClk switching ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/libgfxinit/+/35614/6/common/hw-gfx-gma-registe... File common/hw-gfx-gma-registers.ads:
https://review.coreboot.org/c/libgfxinit/+/35614/6/common/hw-gfx-gma-registe... PS6, Line 1464: DFSM => 16#05_1000# / Register_Width,
Does order matter here? Looks like this offset should go a bit lower.
Order doesn't matter. We could group the fuse stuff together, I guess.
Judging from the very old comment, this group looks just like a heap for registers that didn't find a better place ;)
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/35614 )
Change subject: gma skl: Implement CDClk switching ......................................................................
Patch Set 6: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/libgfxinit/+/35614 )
Change subject: gma skl: Implement CDClk switching ......................................................................
gma skl: Implement CDClk switching
Flow is roughly the same as for Broadwell. Maximum CDClk is now completely controlled by fuses, though. The same frequencies are supported and dot clocks can run at full CDClk speed.
Change-Id: Ic14cf5981540d36d3f337a43bbec3574be0d3c99 Signed-off-by: Nico Huber nico.h@gmx.de Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/35614 Reviewed-by: Matt DeVillier matt.devillier@gmail.com Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M common/hw-gfx-gma-registers.ads M common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb M common/skylake/hw-gfx-gma-power_and_clocks_skylake.ads 3 files changed, 119 insertions(+), 35 deletions(-)
Approvals: Nico Huber: Verified Matt DeVillier: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved
diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 4eb2c04..767284c 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -146,6 +146,7 @@ NDE_RSTWRN_OPT, BLC_PWM_CPU_CTL2, BLC_PWM_CPU_CTL, + DFSM, HTOTAL_A, HBLANK_A, HSYNC_A, @@ -1460,6 +1461,7 @@ PCH_HDMID => 16#0e_1160# / Register_Width,
-- Intel Registers + DFSM => 16#05_1000# / Register_Width, CPU_VGACNTRL => 16#04_1000# / Register_Width, GMCH_VGACNTRL => 16#07_1400# / Register_Width, FUSE_STATUS => 16#04_2000# / Register_Width, diff --git a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb index 2ab7f21..e8087ed 100644 --- a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb +++ b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb @@ -1,5 +1,5 @@ -- --- Copyright (C) 2014-2016 secunet Security Networks AG +-- Copyright (C) 2014-2016, 2019 secunet Security Networks AG -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -34,6 +34,12 @@ FUSE_STATUS_DOWNLOAD_STATUS : constant := 1 * 2 ** 31; FUSE_STATUS_PG0_DIST_STATUS : constant := 1 * 2 ** 27;
+ DFSM_DISPLAY_CDCLK_LIMIT_675MHZ : constant := 0 * 2 ** 23; + DFSM_DISPLAY_CDCLK_LIMIT_540MHZ : constant := 1 * 2 ** 23; + DFSM_DISPLAY_CDCLK_LIMIT_450MHZ : constant := 2 * 2 ** 23; + DFSM_DISPLAY_CDCLK_LIMIT_337_5MHZ : constant := 3 * 2 ** 23; + DFSM_DISPLAY_CDCLK_LIMIT_MASK : constant := 3 * 2 ** 23; + type Power_Domain_Values is array (Power_Domain) of Word32; PWR_WELL_CTL_POWER_REQUEST : constant Power_Domain_Values := (MISC_IO => 1 * 2 ** 1, @@ -87,12 +93,10 @@ SKL_CDCLK_PREPARE_FOR_CHANGE : constant := 3; SKL_CDCLK_READY_FOR_CHANGE : constant := 1;
- function CDCLK_CTL_CD_FREQ_DECIMAL - (Freq : Pos16; - Plus_Half : Boolean) - return Word32 is + function CDCLK_CTL_CD_FREQ_DECIMAL (CDClk : Frequency_Type) return Word32 is begin - return Word32 (2 * (Pos32 (Freq) - 1)) or (if Plus_Half then 1 else 0); + -- Weirdest representation: CDClk - 1MHz in 10.1 (10 + 1 fractional bit) + return Word32 ((CDClk - 1_000_000) / 500_000); end CDCLK_CTL_CD_FREQ_DECIMAL;
---------------------------------------------------------------------------- @@ -232,10 +236,81 @@ PD_Off (PW1); end Post_All_Off;
- procedure Initialize + function Normalize_CDClk (CDClk : in Int64) return Config.CDClk_Range is + ( if CDClk <= 337_500_000 then 337_500_000 + elsif CDClk <= 450_000_000 then 450_000_000 + elsif CDClk <= 540_000_000 then 540_000_000 + else 675_000_000); + + procedure Get_Cur_CDClk (CDClk : out Config.CDClk_Range) is + CDCLK_CTL : Word32; + begin + Registers.Read (Registers.CDCLK_CTL, CDCLK_CTL); + CDCLK_CTL := CDCLK_CTL and CDCLK_CTL_CD_FREQ_DECIMAL_MASK; + CDClk := Normalize_CDClk (Int64 (CDCLK_CTL) * 500_000 + 1_000_000); + end Get_Cur_CDClk; + + procedure Get_Max_CDClk (CDClk : out Config.CDClk_Range) + is + DFSM : Word32; + begin + Registers.Read (Registers.DFSM, DFSM); + CDClk := + (case DFSM and DFSM_DISPLAY_CDCLK_LIMIT_MASK is + when DFSM_DISPLAY_CDCLK_LIMIT_675MHZ => 675_000_000, + when DFSM_DISPLAY_CDCLK_LIMIT_540MHZ => 540_000_000, + when DFSM_DISPLAY_CDCLK_LIMIT_450MHZ => 450_000_000, + when others => 337_500_000); + end Get_Max_CDClk; + + procedure Set_CDClk (CDClk_In : Frequency_Type) + is + CDClk : constant Config.CDClk_Range := + Normalize_CDClk (Frequency_Type'Min (CDClk_In, Config.Max_CDClk)); Success : Boolean; begin + PCode.Mailbox_Request + (MBox => SKL_PCODE_CDCLK_CONTROL, + Command => SKL_CDCLK_PREPARE_FOR_CHANGE, + Reply_Mask => SKL_CDCLK_READY_FOR_CHANGE, + Wait_Ready => True, + Success => Success); + + if not Success then + pragma Debug (Debug.Put_Line + ("ERROR: PCODE not ready for frequency change.")); + return; + end if; + + Registers.Write + (Register => Registers.CDCLK_CTL, + Value => (case CDClk is + when 675_000_000 => CDCLK_CTL_CD_FREQ_SELECT_675MHZ, + when 540_000_000 => CDCLK_CTL_CD_FREQ_SELECT_540MHZ, + when 450_000_000 => CDCLK_CTL_CD_FREQ_SELECT_450MHZ, + when others => CDCLK_CTL_CD_FREQ_SELECT_337_5MHZ) + or CDCLK_CTL_CD_FREQ_DECIMAL (CDClk)); + + PCode.Mailbox_Write + (MBox => SKL_PCODE_CDCLK_CONTROL, + Command => (case CDClk is + when 675_000_000 => 3, + when 540_000_000 => 2, + when 450_000_000 => 1, + when others => 0)); + Registers.Set_Mask + (Register => Registers.DBUF_CTL, + Mask => DBUF_CTL_DBUF_POWER_REQUEST); + Registers.Wait_Set_Mask + (Register => Registers.DBUF_CTL, + Mask => DBUF_CTL_DBUF_POWER_STATE); + + Config.CDClk := CDClk; + end Set_CDClk; + + procedure Initialize is + begin Registers.Set_Mask (Register => Registers.NDE_RSTWRN_OPT, Mask => NDE_RSTWRN_OPT_RST_PCH_Handshake_En); @@ -246,10 +321,6 @@ PD_On (PW1); PD_On (MISC_IO);
- Registers.Write - (Register => Registers.CDCLK_CTL, - Value => CDCLK_CTL_CD_FREQ_SELECT_337_5MHZ or - CDCLK_CTL_CD_FREQ_DECIMAL (337, True)); -- TODO: Set to preferred eDP rate: -- Registers.Unset_And_Set_Mask -- (Register => Registers.DPLL_CTRL1, @@ -262,34 +333,33 @@ (Register => Registers.LCPLL1_CTL, Mask => LCPLL1_CTL_PLL_LOCK);
- PCode.Mailbox_Request - (MBox => SKL_PCODE_CDCLK_CONTROL, - Command => SKL_CDCLK_PREPARE_FOR_CHANGE, - Reply_Mask => SKL_CDCLK_READY_FOR_CHANGE, - Wait_Ready => True, - Success => Success); - - pragma Debug (not Success, Debug.Put_Line - ("ERROR: PCODE not ready for frequency change.")); - - if Success then - PCode.Mailbox_Write - (MBox => SKL_PCODE_CDCLK_CONTROL, - Command => 16#0000_0000#); -- 0 - 337.5MHz - -- 1 - 450.0MHz - -- 2 - 540.0MHz - -- 3 - 675.0MHz - Registers.Set_Mask - (Register => Registers.DBUF_CTL, - Mask => DBUF_CTL_DBUF_POWER_REQUEST); - Registers.Wait_Set_Mask - (Register => Registers.DBUF_CTL, - Mask => DBUF_CTL_DBUF_POWER_STATE); - end if; + Get_Cur_CDClk (Config.CDClk); + Get_Max_CDClk (Config.Max_CDClk); + Set_CDClk (Config.Default_CDClk_Freq);
Config.Raw_Clock := Config.Default_RawClk_Freq; end Initialize;
+ procedure Limit_Dotclocks + (Configs : in out Pipe_Configs; + CDClk_Switch : out Boolean) + is + begin + Config_Helpers.Limit_Dotclocks (Configs, Config.Max_CDClk); + CDClk_Switch := + Config.CDClk /= Normalize_CDClk + (Config_Helpers.Highest_Dotclock (Configs)); + end Limit_Dotclocks; + + procedure Update_CDClk (Configs : in out Pipe_Configs) + is + New_CDClk : constant Frequency_Type := + Config_Helpers.Highest_Dotclock (Configs); + begin + Set_CDClk (New_CDClk); + Config_Helpers.Limit_Dotclocks (Configs, Config.CDClk); + end Update_CDClk; + procedure Power_Set_To (Configs : Pipe_Configs) is begin for PD in reverse Dynamic_Domain loop diff --git a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.ads b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.ads index 4db9ab5..d5b9685 100644 --- a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.ads +++ b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.ads @@ -12,6 +12,8 @@ -- GNU General Public License for more details. --
+with HW.GFX.GMA.Config_Helpers; + private package HW.GFX.GMA.Power_And_Clocks_Skylake is
procedure Pre_All_Off; @@ -19,6 +21,16 @@
procedure Initialize;
+ procedure Limit_Dotclocks + (Configs : in out Pipe_Configs; + CDClk_Switch : out Boolean) + with + Post => Config_Helpers.Stable_FB (Configs'Old, Configs); + procedure Update_CDClk (Configs : in out Pipe_Configs) + with + Post => Config_Helpers.Stable_FB (Configs'Old, Configs); + procedure Enable_CDClk is null; + procedure Power_Set_To (Configs : Pipe_Configs); procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs); procedure Power_Down (Old_Configs, Tmp_Configs, New_Configs : Pipe_Configs);
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Matt DeVillier (Code Review)
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Nico Huber (Code Review)