Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80361?usp=email )
Change subject: soc/intel/cmn/sa: Refactor SA common code ......................................................................
soc/intel/cmn/sa: Refactor SA common code
Leverages common SA header definitions for Host Bridge registers. Renames DSM_BASE_ADDR_REG to BDSM and DPR_REG to DPR for brevity.
TEST= Build and boot successful on google/screebo.
Change-Id: I476f213d75a0978336b3749a5ba1499107eb2238 Signed-off-by: Subrata Banik subratabanik@google.com --- M src/soc/intel/alderlake/include/soc/systemagent.h M src/soc/intel/alderlake/systemagent.c M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/meteorlake/include/soc/systemagent.h M src/soc/intel/meteorlake/systemagent.c 6 files changed, 19 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/80361/1
diff --git a/src/soc/intel/alderlake/include/soc/systemagent.h b/src/soc/intel/alderlake/include/soc/systemagent.h index 36d3398..0d9e1b2 100644 --- a/src/soc/intel/alderlake/include/soc/systemagent.h +++ b/src/soc/intel/alderlake/include/soc/systemagent.h @@ -66,15 +66,12 @@
#define MASK_PCIEXBAR_LENGTH 0x0000000E // bits [3:1] #define PCIEXBAR_LENGTH_LSB 1 // used to shift right - -#define DSM_BASE_ADDR_REG 0xB0 -#define MASK_DSM_LENGTH 0xFF00 // [15:8] -#define MASK_DSM_LENGTH_LSB 8 // used to shift right -#define MASK_GSM_LENGTH 0xC0 // [7:6] -#define MASK_GSM_LENGTH_LSB 6 // used to shift right -#define DPR_REG 0x5C -#define MASK_DPR_LENGTH 0xFF0 // [11:4] -#define MASK_DPR_LENGTH_LSB 4 // used to shift right +#define MASK_DSM_LENGTH 0xFF00 // [15:8] +#define MASK_DSM_LENGTH_LSB 8 // used to shift right +#define MASK_GSM_LENGTH 0xC0 // [7:6] +#define MASK_GSM_LENGTH_LSB 6 // used to shift right +#define MASK_DPR_LENGTH 0xFF0 // [11:4] +#define MASK_DPR_LENGTH_LSB 4 // used to shift right
uint64_t get_mmcfg_size(const struct device *dev); uint64_t get_dsm_size(const struct device *dev); diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c index 36fa45b..ecd704e 100644 --- a/src/soc/intel/alderlake/systemagent.c +++ b/src/soc/intel/alderlake/systemagent.c @@ -111,7 +111,7 @@ /* DSM */ size = get_dsm_size(dev); if (size > 0) { - base = pci_read_config32(dev, DSM_BASE_ADDR_REG) & 0xFFF00000; + base = pci_read_config32(dev, BDSM) & 0xFFF00000; set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DSM"); }
@@ -316,7 +316,7 @@ uint64_t get_dpr_size(const struct device *dev) { uint64_t size; - uint32_t dpr_reg = pci_read_config32(dev, DPR_REG); + uint32_t dpr_reg = pci_read_config32(dev, DPR); uint32_t size_field = (dpr_reg & MASK_DPR_LENGTH) >> MASK_DPR_LENGTH_LSB; size = (uint64_t)size_field * MiB; return size; diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index 64e9be6..d817e9c 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -34,6 +34,9 @@ #define G_GGMS_OFFSET 0x6 #define G_GGMS_MASK 0xc0
+/* DMA Protected Range Register */ +#define DPR 0x5C + /* MCHBAR */ #define MCHBAR8(x) (*(volatile u8 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) #define MCHBAR16(x) (*(volatile u16 *)(uintptr_t)(MCH_BASE_ADDRESS + x)) diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index 09a99ea..f913843 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -5,9 +5,7 @@
/* Device 0:0.0 PCI configuration space */
- /* DPR register in case CONFIG_SA_ENABLE_DPR is selected by SoC */ -#define DPR 0x5c #define DPR_EPM (1 << 2) #define DPR_PRS (1 << 1) #define DPR_SIZE_MASK 0xff0 diff --git a/src/soc/intel/meteorlake/include/soc/systemagent.h b/src/soc/intel/meteorlake/include/soc/systemagent.h index d463ce1..4196548 100644 --- a/src/soc/intel/meteorlake/include/soc/systemagent.h +++ b/src/soc/intel/meteorlake/include/soc/systemagent.h @@ -52,15 +52,12 @@
#define MASK_PCIEXBAR_LENGTH 0x0000000E // bits [3:1] #define PCIEXBAR_LENGTH_LSB 1 // used to shift right - -#define DSM_BASE_ADDR_REG 0xB0 -#define MASK_DSM_LENGTH 0xFF00 // [15:8] -#define MASK_DSM_LENGTH_LSB 8 // used to shift right -#define MASK_GSM_LENGTH 0xC0 // [7:6] -#define MASK_GSM_LENGTH_LSB 6 // used to shift right -#define DPR_REG 0x5C -#define MASK_DPR_LENGTH 0xFF0 // [11:4] -#define MASK_DPR_LENGTH_LSB 4 // used to shift right +#define MASK_DSM_LENGTH 0xFF00 // [15:8] +#define MASK_DSM_LENGTH_LSB 8 // used to shift right +#define MASK_GSM_LENGTH 0xC0 // [7:6] +#define MASK_GSM_LENGTH_LSB 6 // used to shift right +#define MASK_DPR_LENGTH 0xFF0 // [11:4] +#define MASK_DPR_LENGTH_LSB 4 // used to shift right
uint64_t get_mmcfg_size(const struct device *dev); uint64_t get_dsm_size(const struct device *dev); diff --git a/src/soc/intel/meteorlake/systemagent.c b/src/soc/intel/meteorlake/systemagent.c index 875ddcc..a6c8c71 100644 --- a/src/soc/intel/meteorlake/systemagent.c +++ b/src/soc/intel/meteorlake/systemagent.c @@ -103,7 +103,7 @@ /* DSM */ size = get_dsm_size(dev); if (size > 0) { - base = pci_read_config32(dev, DSM_BASE_ADDR_REG) & 0xFFF00000; + base = pci_read_config32(dev, BDSM) & 0xFFF00000; set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DSM"); }
@@ -325,7 +325,7 @@ uint64_t get_dpr_size(const struct device *dev) { uint64_t size; - uint32_t dpr_reg = pci_read_config32(dev, DPR_REG); + uint32_t dpr_reg = pci_read_config32(dev, DPR); uint32_t size_field = (dpr_reg & MASK_DPR_LENGTH) >> MASK_DPR_LENGTH_LSB; size = (uint64_t)size_field * MiB; return size;