Attention is currently required from: Sridhar Siricilla, Paul Menzel, Ravindra, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55363 )
Change subject: soc/intel/common: Add HECI Reset flow in the CSE driver ......................................................................
Patch Set 7:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55363/comment/b32824ca_ef4e9166 PS2, Line 8:
Please start by stating the problem.
Done
https://review.coreboot.org/c/coreboot/+/55363/comment/c5a300e3_74d57616 PS2, Line 9: This is required as part : of the HECI Interface initialization in order to put the host and CSE into : a known good state for communication.
Please reference the specification.
Done
https://review.coreboot.org/c/coreboot/+/55363/comment/5eabee31_1ed4b686 PS2, Line 15:
Is there bug for this?
There is no bug.
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/55363/comment/5507b3a3_38904044 PS2, Line 104: Triggers
Imperative mood: Trigger.
Done
https://review.coreboot.org/c/coreboot/+/55363/comment/2ca5511a_050e482a PS2, Line 104: makes
make
Done
https://review.coreboot.org/c/coreboot/+/55363/comment/9cb8ea0d_ff42ea46 PS2, Line 105: heci_reset();
I notice heci_reset()is taking maximum of 1ms and min of 0.2ms in my tests. […]
Done