Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports

[Benjamin Doron (Code Review)]

Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39538

to look at the new patch set (#25).

Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports
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soc/intel/skylake: Configure L1 substates for PCH root ports

Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration.

Tested on an Acer Aspire VN7-572G (Skylake-U).

Change-Id: I36150858485715016158595c832c142b0582ddb8
Signed-off-by: Benjamin Doron 
---
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
2 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/25