Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Jason Glenesk, Matt Delco, Marshall Dawson, Tim Wawrzynczak, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57886 )
Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table ......................................................................
Patch Set 11:
(15 comments)
File src/cpu/intel/common/common_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151): https://review.coreboot.org/c/coreboot/+/57886/comment/b5253dc4_12fab34d PS11, Line 108: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151): https://review.coreboot.org/c/coreboot/+/57886/comment/acb4dc7f_ceceb7b6 PS11, Line 110: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151): https://review.coreboot.org/c/coreboot/+/57886/comment/7a870c69_1ff8738d PS11, Line 111: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151): https://review.coreboot.org/c/coreboot/+/57886/comment/5262abae_b08a1c13 PS11, Line 112: config->entries[CPPC_GUARANTEED_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151): https://review.coreboot.org/c/coreboot/+/57886/comment/dd060bbf_95f6e983 PS11, Line 128: config->entries[CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_REG_MSR(IA32_HWP_REQUEST, 32, 10); line over 96 characters
File src/soc/amd/cezanne/cppc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151): https://review.coreboot.org/c/coreboot/+/57886/comment/b3d4c683_23aab728 PS11, Line 18: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151): https://review.coreboot.org/c/coreboot/+/57886/comment/fe80531e_00823cc1 PS11, Line 19: config->entries[CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151): https://review.coreboot.org/c/coreboot/+/57886/comment/962f75ad_4ef0a18c PS11, Line 20: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151): https://review.coreboot.org/c/coreboot/+/57886/comment/c66d378a_5245d57d PS11, Line 21: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151): https://review.coreboot.org/c/coreboot/+/57886/comment/6e602a10_ad5df217 PS11, Line 23: config->entries[CPPC_DESIRED_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151): https://review.coreboot.org/c/coreboot/+/57886/comment/3f1aeb3e_c2650f96 PS11, Line 24: config->entries[CPPC_MIN_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151): https://review.coreboot.org/c/coreboot/+/57886/comment/e160f136_8a2ac75b PS11, Line 25: config->entries[CPPC_MAX_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151): https://review.coreboot.org/c/coreboot/+/57886/comment/21e2cdca_e395d018 PS11, Line 29: config->entries[CPPC_REF_PERF_COUNTER] = CPPC_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151): https://review.coreboot.org/c/coreboot/+/57886/comment/e9d4002d_56d74c26 PS11, Line 30: config->entries[CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130151): https://review.coreboot.org/c/coreboot/+/57886/comment/c4d3707b_2459c366 PS11, Line 39: config->entries[CPPC_PERF_PREF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8); line over 96 characters