Change in coreboot[master]: soc/intel/soc: Remove save state handler code - coreboot-gerrit

17 Sep 2020

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45477 )
Change subject: soc/intel/soc: Remove save state handler code
......................................................................
soc/intel/soc: Remove save state handler code
Change-Id: I08349fd4f8d0a3dcd64f70ddfc9d18abcafb9d3b
Signed-off-by: Arthur Heymans arthur@aheymans.xyz
---
M src/soc/intel/apollolake/smihandler.c
M src/soc/intel/baytrail/smihandler.c
M src/soc/intel/braswell/smihandler.c
M src/soc/intel/broadwell/smihandler.c
M src/soc/intel/cannonlake/smihandler.c
M src/soc/intel/common/block/include/intelblocks/smihandler.h
M src/soc/intel/common/block/smm/smihandler.c
M src/soc/intel/common/block/smm/smitraphandler.c
M src/soc/intel/denverton_ns/smihandler.c
M src/soc/intel/icelake/smihandler.c
M src/soc/intel/jasperlake/smihandler.c
M src/soc/intel/skylake/smihandler.c
M src/soc/intel/tigerlake/smihandler.c
M src/southbridge/intel/common/smihandler.c
M src/southbridge/intel/lynxpoint/smihandler.c
15 files changed, 54 insertions(+), 461 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45477/1

diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c
index bcbc819..ddde65d 100644
--- a/src/soc/intel/apollolake/smihandler.c
+++ b/src/soc/intel/apollolake/smihandler.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
#include <cpu/x86/smm.h>
-#include <cpu/intel/em64t100_save_state.h>
 #include <intelblocks/smihandler.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>
@@ -15,12 +14,7 @@
    return 1;
 }
-const struct smm_save_state_ops *get_smm_save_state_ops(void)
-{
-	return &em64t100_smm_ops;
-}
-
-const smi_handler_t southbridge_smi[32] = {
+const void (*southbridge_smi[32])(void) = {
    [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
    [APM_STS_BIT] = smihandler_southbridge_apmc,
    [PM1_STS_BIT] = smihandler_southbridge_pm1,
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 9348ae0..0372e81 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -6,7 +6,7 @@
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
-#include <cpu/intel/em64t100_save_state.h>
+#include <cpu/x86/save_state.h>
 #include <device/pci_def.h>
 #include <elog.h>
 #include <halt.h>
@@ -152,41 +152,6 @@
 }
/*
- * Look for Synchronous IO SMI and use save state from that core in case
- * we are not running on the same core that initiated the IO transaction.
- */
-static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
-{
-	em64t100_smm_state_save_area_t *state;
-	int node;
-
-	/* Check all nodes looking for the one that issued the IO */
-	for (node = 0; node < CONFIG_MAX_CPUS; node++) {
-		state = smm_get_save_state(node);
-
-		/* Check for Synchronous IO (bit0==1) */
-		if (!(state->io_misc_info & (1 << 0)))
-			continue;
-
-		/* Make sure it was a write (bit4==0) */
-		if (state->io_misc_info & (1 << 4))
-			continue;
-
-		/* Check for APMC IO port */
-		if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)
-			continue;
-
-		/* Check AX against the requested command */
-		if ((state->rax & 0xff) != cmd)
-			continue;
-
-		return state;
-	}
-
-	return NULL;
-}
-
-/*
  * soc_legacy: A payload (Depthcharge) has indicated that the
  *   legacy payload (SeaBIOS) is being loaded. Switch devices that are
  *   in ACPI mode to PCI mode so that non-ACPI drivers may work.
@@ -278,11 +243,10 @@
    		printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
    		return;
    	}
-		state = smi_apmc_find_state_save(reg8);
-		if (state) {
-			/* EBX in the state save contains the GNVS pointer */
-			gnvs = (struct global_nvs *)((uint32_t)state->rbx);
-			smm_initialized = 1;
+		int node = get_apmc_node(reg8);
+		if (node >= 0) {
+			if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs)))
+				smm_initialized = 1;
    		printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
    	}
    	break;
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index 6f8cd62..b9ba4d8 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -7,7 +7,7 @@
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
-#include <cpu/intel/em64t100_save_state.h>
+#include <cpu/x86/save_state.h>
 #include <device/pci_def.h>
 #include <elog.h>
 #include <soc/nvs.h>
@@ -185,41 +185,6 @@
    }
 }
-/*
- * Look for Synchronous IO SMI and use save state from that core in case
- * we are not running on the same core that initiated the IO transaction.
- */
-static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
-{
-	em64t100_smm_state_save_area_t *state;
-	int node;
-
-	/* Check all nodes looking for the one that issued the IO */
-	for (node = 0; node < CONFIG_MAX_CPUS; node++) {
-		state = smm_get_save_state(node);
-
-		/* Check for Synchronous IO (bit0==1) */
-		if (!(state->io_misc_info & (1 << 0)))
-			continue;
-
-		/* Make sure it was a write (bit4==0) */
-		if (state->io_misc_info & (1 << 4))
-			continue;
-
-		/* Check for APMC IO port */
-		if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)
-			continue;
-
-		/* Check AX against the requested command */
-		if ((state->rax & 0xff) != cmd)
-			continue;
-
-		return state;
-	}
-
-	return NULL;
-}
-
 static void southbridge_smi_apmc(void)
 {
    uint8_t reg8;
@@ -258,11 +223,10 @@
    		printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
    		return;
    	}
-		state = smi_apmc_find_state_save(reg8);
-		if (state) {
-			/* EBX in the state save contains the GNVS pointer */
-			gnvs = (struct global_nvs *)((uint32_t)state->rbx);
-			smm_initialized = 1;
+		int node = get_apmc_node(reg8);
+		if (node >= 0) {
+			if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs)))
+				smm_initialized = 1;
    		printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
    	}
    	break;
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index a223bf5..0ccdc5b 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -9,7 +9,7 @@
 #include <cpu/x86/cache.h>
 #include <device/pci_def.h>
 #include <cpu/x86/smm.h>
-#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/x86/save_state.h>
 #include <spi-generic.h>
 #include <elog.h>
 #include <halt.h>
@@ -231,46 +231,9 @@
    }
 }
-/*
- * Look for Synchronous IO SMI and use save state from that
- * core in case we are not running on the same core that
- * initiated the IO transaction.
- */
-static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
-{
-	em64t101_smm_state_save_area_t *state;
-	int node;
-
-	/* Check all nodes looking for the one that issued the IO */
-	for (node = 0; node < CONFIG_MAX_CPUS; node++) {
-		state = smm_get_save_state(node);
-
-		/* Check for Synchronous IO (bit0==1) */
-		if (!(state->io_misc_info & (1 << 0)))
-			continue;
-
-		/* Make sure it was a write (bit4==0) */
-		if (state->io_misc_info & (1 << 4))
-			continue;
-
-		/* Check for APMC IO port */
-		if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)
-			continue;
-
-		/* Check AX against the requested command */
-		if ((state->rax & 0xff) != cmd)
-			continue;
-
-		return state;
-	}
-
-	return NULL;
-}
-
 static void southbridge_smi_apmc(void)
 {
    u8 reg8;
-	em64t101_smm_state_save_area_t *state;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -296,11 +259,10 @@
    		       "SMI#: SMM structures already initialized!\n");
    		return;
    	}
-		state = smi_apmc_find_state_save(reg8);
-		if (state) {
-			/* EBX in the state save contains the GNVS pointer */
-			gnvs = (struct global_nvs *)((u32)state->rbx);
-			smm_initialized = 1;
+		int node = get_apmc_node(reg8);
+		if (node >= 0) {
+			if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs)))
+				smm_initialized = 1;
    		printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
    	}
    	break;
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c
index 266c258..4ba142e 100644
--- a/src/soc/intel/cannonlake/smihandler.c
+++ b/src/soc/intel/cannonlake/smihandler.c
@@ -25,7 +25,7 @@
    	heci_disable();
 }
-const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+const void (*southbridge_smi[SMI_STS_BITS])(void) = {
    [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
    [APM_STS_BIT] = smihandler_southbridge_apmc,
    [PM1_STS_BIT] = smihandler_southbridge_pm1,
diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h
index 7cea1dd..7ebd31c 100644
--- a/src/soc/intel/common/block/include/intelblocks/smihandler.h
+++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h
@@ -10,41 +10,11 @@
 struct global_nvs;
/*
- * The register value is used with get_reg and set_reg
- */
-enum smm_reg {
-	RAX,
-	RBX,
-	RCX,
-	RDX,
-};
-
-struct smm_save_state_ops {
-	/* return io_misc_info from SMM Save State Area */
-	uint32_t (*get_io_misc_info)(void *state);
-
-	/* return value of the requested register from
-	 * SMM Save State Area
-	 */
-	uint64_t (*get_reg)(void *state, enum smm_reg reg);
-
-	void (*set_reg)(void *state, enum smm_reg reg, uint64_t val);
-};
-
-typedef void (*smi_handler_t)(const struct smm_save_state_ops *save_state_ops);
-
-/*
- * SOC SMI Handler has to provide this structure which has methods to access
- * the SOC specific SMM Save State Area
- */
-const struct smm_save_state_ops *get_smm_save_state_ops(void);
-
-/*
  * southbridge_smi should be defined inside SOC specific code and should have
  * handlers for any SMI events that need to be handled. Default handlers
  * for some SMI events are provided in soc/intel/common/block/smm/smihandler.c
  */
-extern const smi_handler_t southbridge_smi[32];
+extern const void (*southbridge_smi[32])(void);
#define SMI_HANDLER_SCI_EN(__bit)	(1 << (__bit))
@@ -53,79 +23,69 @@
  * the SMI event on SLP_EN. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_sleep(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_sleep(void);
/*
  * This function should be implemented in SOC specific code to handle
  * SMI_APM event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_apmc(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_apmc(void);
/*
  * This function should be implemented in SOC specific code to handle
  * SMI_PM1 event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_pm1(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_pm1(void);
/*
  * This function should be implemented in SOC specific code to handle
  * SMI_GPE0 event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_gpe0(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_gpe0(void);
/*
  * This function should be implemented in SOC specific code to handle
  * MC event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_mc(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_mc(void);
/*
  * This function should be implemented in SOC specific code to handle
  * minitor event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_monitor(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_monitor(void);
 /*
  * This function should be implemented in SOC specific code to handle
  * SMI_TCO event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_tco(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_tco(void);
/*
  * This function should be implemented in SOC specific code to handle
  * SMI PERIODIC_STS event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_periodic(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_periodic(void);
/*
  * This function should be implemented in SOC specific code to handle
  * SMI GPIO_STS event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_gpi(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_gpi(void);
/*
  * This function should be implemented in SOC specific code to handle
  * SMI ESPI_STS event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_espi(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_espi(void);
/* SoC overrides. */
@@ -145,8 +105,4 @@
/* Mainboard handler for ESPI EMIs */
 void mainboard_smi_espi_handler(void);
-
-extern const struct smm_save_state_ops em64t100_smm_ops;
-
-extern const struct smm_save_state_ops em64t101_smm_ops;
 #endif
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index b629ef2..d1b9093 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -6,8 +6,7 @@
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
-#include <cpu/intel/em64t100_save_state.h>
-#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/x86/save_state.h>
 #include <delay.h>
 #include <device/pci_def.h>
 #include <elog.h>
@@ -26,13 +25,6 @@
 #include <spi-generic.h>
 #include <stdint.h>
-/* SoC overrides. */
-
-__weak const struct smm_save_state_ops *get_smm_save_state_ops(void)
-{
-	return &em64t101_smm_ops;
-}
-
 /* Specific SOC SMI handler during ramstage finalize phase */
 __weak void smihandler_soc_at_finalize(void)
 {
@@ -84,38 +76,6 @@
/* Common Functions */
-static void *find_save_state(const struct smm_save_state_ops *save_state_ops,
-	int cmd)
-{
-	int node;
-	void *state = NULL;
-	uint32_t io_misc_info;
-	uint8_t reg_al;
-
-	/* Check all nodes looking for the one that issued the IO */
-	for (node = 0; node < CONFIG_MAX_CPUS; node++) {
-		state = smm_get_save_state(node);
-
-		io_misc_info = save_state_ops->get_io_misc_info(state);
-
-		/* Check for Synchronous IO (bit0==1) */
-		if (!(io_misc_info & (1 << 0)))
-			continue;
-		/* Make sure it was a write (bit4==0) */
-		if (io_misc_info & (1 << 4))
-			continue;
-		/* Check for APMC IO port */
-		if (((io_misc_info >> 16) & 0xff) != APM_CNT)
-			continue;
-		/* Check AL against the requested command */
-		reg_al = save_state_ops->get_reg(state, RAX);
-		if (reg_al != cmd)
-			continue;
-		break;
-	}
-	return state;
-}
-
 /* Inherited from cpu/x86/smm.h resulting in a different signature */
 void southbridge_smi_set_eos(void)
 {
@@ -170,8 +130,7 @@
 }
-void smihandler_southbridge_sleep(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_sleep(void)
 {
    uint32_t reg32;
    uint8_t slp_typ;
@@ -284,11 +243,9 @@
    smihandler_soc_at_finalize();
 }
-void smihandler_southbridge_apmc(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_apmc(void)
 {
    uint8_t reg8;
-	void *state = NULL;
    static int smm_initialized = 0;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -325,12 +282,10 @@
    		       "SMI#: SMM structures already initialized!\n");
    		return;
    	}
-		state = find_save_state(save_state_ops, reg8);
-		if (state) {
-			/* EBX in the state save contains the GNVS pointer */
-			uint32_t reg_ebx = save_state_ops->get_reg(state, RBX);
-			gnvs = (struct global_nvs *)(uintptr_t)reg_ebx;
-			smm_initialized = 1;
+		int node = get_apmc_node(reg8);
+		if (node >= 0) {
+			if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs)))
+				smm_initialized = 1;
    		printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
    	}
    	break;
@@ -350,8 +305,7 @@
    mainboard_smi_apmc(reg8);
 }
-void smihandler_southbridge_pm1(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_pm1(void)
 {
    uint16_t pm1_sts = pmc_clear_pm1_status();
    u16 pm1_en = pmc_read_pm1_enable();
@@ -368,14 +322,12 @@
    }
 }
-void smihandler_southbridge_gpe0(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_gpe0(void)
 {
    pmc_clear_all_gpe_status();
 }
-void smihandler_southbridge_tco(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_tco(void)
 {
    uint32_t tco_sts = pmc_clear_tco_status();
@@ -399,8 +351,7 @@
    }
 }
-void smihandler_southbridge_periodic(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_periodic(void)
 {
    uint32_t reg32;
@@ -412,8 +363,7 @@
    printk(BIOS_DEBUG, "Periodic SMI.\n");
 }
-void smihandler_southbridge_gpi(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_gpi(void)
 {
    struct gpi_status smi_sts;
@@ -424,8 +374,7 @@
    gpi_clear_get_smi_status(&smi_sts);
 }
-void smihandler_southbridge_espi(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_espi(void)
 {
    mainboard_smi_espi_handler();
 }
@@ -444,7 +393,6 @@
 {
    int i;
    uint32_t smi_sts;
-	const struct smm_save_state_ops *save_state_ops;
/*
     * We need to clear the SMI status registers, or we won't see what's
@@ -463,15 +411,13 @@
    if (!smi_sts)
    	return;
-	save_state_ops = get_smm_save_state_ops();
-
    /* Call SMI sub handler for each of the status bits */
    for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {
    	if (!(smi_sts & (1 << i)))
    		continue;
if (southbridge_smi[i] != NULL) {
-			southbridge_smi[i](save_state_ops);
+			southbridge_smi[i]();
    	} else {
    		printk(BIOS_DEBUG,
    		       "SMI_STS[%d] occurred, but no "
@@ -479,119 +425,3 @@
    	}
    }
 }
-
-static uint32_t em64t100_smm_save_state_get_io_misc_info(void *state)
-{
-	em64t100_smm_state_save_area_t *smm_state = state;
-	return smm_state->io_misc_info;
-}
-
-static uint64_t em64t100_smm_save_state_get_reg(void *state, enum smm_reg reg)
-{
-	uintptr_t value = 0;
-	em64t100_smm_state_save_area_t *smm_state = state;
-
-	switch (reg) {
-	case RAX:
-		value = smm_state->rax;
-		break;
-	case RBX:
-		value = smm_state->rbx;
-		break;
-	case RCX:
-		value = smm_state->rcx;
-		break;
-	case RDX:
-		value = smm_state->rdx;
-		break;
-	default:
-		break;
-	}
-	return value;
-}
-
-static void em64t100_smm_save_state_set_reg(void *state, enum smm_reg reg,
-	uint64_t val)
-{
-	em64t100_smm_state_save_area_t *smm_state = state;
-	switch (reg) {
-	case RAX:
-		smm_state->rax = val;
-		break;
-	case RBX:
-		smm_state->rbx = val;
-		break;
-	case RCX:
-		smm_state->rcx = val;
-		break;
-	case RDX:
-		smm_state->rdx = val;
-		break;
-	default:
-		break;
-	}
-}
-
-static uint32_t em64t101_smm_save_state_get_io_misc_info(void *state)
-{
-	em64t101_smm_state_save_area_t *smm_state = state;
-	return smm_state->io_misc_info;
-}
-
-static uint64_t em64t101_smm_save_state_get_reg(void *state, enum smm_reg reg)
-{
-	uintptr_t value = 0;
-	em64t101_smm_state_save_area_t *smm_state = state;
-
-	switch (reg) {
-	case RAX:
-		value = smm_state->rax;
-		break;
-	case RBX:
-		value = smm_state->rbx;
-		break;
-	case RCX:
-		value = smm_state->rcx;
-		break;
-	case RDX:
-		value = smm_state->rdx;
-		break;
-	default:
-		break;
-	}
-	return value;
-}
-
-static void em64t101_smm_save_state_set_reg(void *state, enum smm_reg reg,
-	uint64_t val)
-{
-	em64t101_smm_state_save_area_t *smm_state = state;
-	switch (reg) {
-	case RAX:
-		smm_state->rax = val;
-		break;
-	case RBX:
-		smm_state->rbx = val;
-		break;
-	case RCX:
-		smm_state->rcx = val;
-		break;
-	case RDX:
-		smm_state->rdx = val;
-		break;
-	default:
-		break;
-	}
-}
-
-const struct smm_save_state_ops em64t100_smm_ops = {
-	.get_io_misc_info = em64t100_smm_save_state_get_io_misc_info,
-	.get_reg = em64t100_smm_save_state_get_reg,
-	.set_reg = em64t100_smm_save_state_set_reg,
-};
-
-const struct smm_save_state_ops em64t101_smm_ops = {
-	.get_io_misc_info = em64t101_smm_save_state_get_io_misc_info,
-	.get_reg = em64t101_smm_save_state_get_reg,
-	.set_reg = em64t101_smm_save_state_set_reg,
-};
diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c
index 99825f1..6900061 100644
--- a/src/soc/intel/common/block/smm/smitraphandler.c
+++ b/src/soc/intel/common/block/smm/smitraphandler.c
@@ -40,8 +40,7 @@
    return 0;
 }
-void smihandler_southbridge_mc(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_mc(void)
 {
    u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN);
@@ -52,8 +51,7 @@
    printk(BIOS_DEBUG, "Microcontroller SMI.\n");
 }
-void smihandler_southbridge_monitor(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_monitor(void)
 {
 #define IOTRAP(x) (trap_sts & (1 << x))
    u32 trap_cycle;
diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c
index 5eecba7..397a6ec 100644
--- a/src/soc/intel/denverton_ns/smihandler.c
+++ b/src/soc/intel/denverton_ns/smihandler.c
@@ -7,7 +7,7 @@
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
-#include <cpu/intel/em64t100_save_state.h>
+#include <cpu/x86/save_state.h>
 #include <device/pci_def.h>
 #include <intelblocks/fast_spi.h>
 #include <spi-generic.h>
@@ -146,42 +146,6 @@
    }
 }
-/*
- * Look for Synchronous IO SMI and use save state from that
- * core in case we are not running on the same core that
- * initiated the IO transaction.
- */
-static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
-{
-	em64t100_smm_state_save_area_t *state;
-	int node;
-
-	/* Check all nodes looking for the one that issued the IO */
-	for (node = 0; node < CONFIG_MAX_CPUS; node++) {
-		state = smm_get_save_state(node);
-
-		/* Check for Synchronous IO (bit0==1) */
-		if (!(state->io_misc_info & (1 << 0)))
-			continue;
-
-		/* Make sure it was a write (bit4==0) */
-		if (state->io_misc_info & (1 << 4))
-			continue;
-
-		/* Check for APMC IO port */
-		if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)
-			continue;
-
-		/* Check AX against the requested command */
-		if ((state->rax & 0xff) != cmd)
-			continue;
-
-		return state;
-	}
-
-	return NULL;
-}
-
 static void finalize(void)
 {
    static int finalize_done;
@@ -237,14 +201,12 @@
    		       "SMI#: SMM structures already initialized!\n");
    		return;
    	}
-		state = smi_apmc_find_state_save(reg8);
-		if (state) {
-			/* EBX in the state save contains the GNVS pointer */
-			gnvs = (struct global_nvs *)((uint32_t)state->rbx);
-			smm_initialized = 1;
+		int node = get_apmc_node(reg8);
+		if (node >= 0) {
+			if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs)))
+				smm_initialized = 1;
    		printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
    	}
-		break;
    }
mainboard_smi_apmc(reg8);
diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c
index fbbbbdb..8ff0e6e 100644
--- a/src/soc/intel/icelake/smihandler.c
+++ b/src/soc/intel/icelake/smihandler.c
@@ -25,7 +25,7 @@
    	heci_disable();
 }
-const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+const void (*southbridge_smi[SMI_STS_BITS])(void) = {
    [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
    [APM_STS_BIT] = smihandler_southbridge_apmc,
    [PM1_STS_BIT] = smihandler_southbridge_pm1,
diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c
index 6d31adf..4246b27 100644
--- a/src/soc/intel/jasperlake/smihandler.c
+++ b/src/soc/intel/jasperlake/smihandler.c
@@ -25,7 +25,7 @@
    	heci_disable();
 }
-const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+const void (*southbridge_smi[SMI_STS_BITS])(void) = {
    [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
    [APM_STS_BIT] = smihandler_southbridge_apmc,
    [PM1_STS_BIT] = smihandler_southbridge_pm1,
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c
index 177010c..5df890c 100644
--- a/src/soc/intel/skylake/smihandler.c
+++ b/src/soc/intel/skylake/smihandler.c
@@ -3,7 +3,7 @@
 #include <intelblocks/smihandler.h>
 #include <soc/pm.h>
-const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+const void (*southbridge_smi[SMI_STS_BITS])(void) = {
    [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
    [APM_STS_BIT] = smihandler_southbridge_apmc,
    [PM1_STS_BIT] = smihandler_southbridge_pm1,
diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c
index 40ed25e..a757cca 100644
--- a/src/soc/intel/tigerlake/smihandler.c
+++ b/src/soc/intel/tigerlake/smihandler.c
@@ -25,7 +25,7 @@
    	heci_disable();
 }
-const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+const void (*southbridge_smi[SMI_STS_BITS])(void)
    [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
    [APM_STS_BIT] = smihandler_southbridge_apmc,
    [PM1_STS_BIT] = smihandler_southbridge_pm1,
diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c
index cb42832..bc4896a 100644
--- a/src/southbridge/intel/common/smihandler.c
+++ b/src/southbridge/intel/common/smihandler.c
@@ -269,7 +269,6 @@
    		return;
    	}
    	int node = get_apmc_node(reg8);
-
    	if (node >= 0) {
    		if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs)))
    			smm_initialized = 1;
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 007b383..14f45da 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -7,7 +7,7 @@
 #include <cpu/x86/cache.h>
 #include <device/pci_def.h>
 #include <cpu/x86/smm.h>
-#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/x86/save_state.h>
 #include <elog.h>
 #include <halt.h>
 #include <option.h>
@@ -182,42 +182,6 @@
    }
 }
-/*
- * Look for Synchronous IO SMI and use save state from that
- * core in case we are not running on the same core that
- * initiated the IO transaction.
- */
-static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
-{
-	em64t101_smm_state_save_area_t *state;
-	int node;
-
-	/* Check all nodes looking for the one that issued the IO */
-	for (node = 0; node < CONFIG_MAX_CPUS; node++) {
-		state = smm_get_save_state(node);
-
-		/* Check for Synchronous IO (bit0 == 1) */
-		if (!(state->io_misc_info & (1 << 0)))
-			continue;
-
-		/* Make sure it was a write (bit4 == 0) */
-		if (state->io_misc_info & (1 << 4))
-			continue;
-
-		/* Check for APMC IO port */
-		if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)
-			continue;
-
-		/* Check AX against the requested command */
-		if ((state->rax & 0xff) != cmd)
-			continue;
-
-		return state;
-	}
-
-	return NULL;
-}
-
 static void southbridge_smi_apmc(void)
 {
    u8 reg8;
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I08349fd4f8d0a3dcd64f70ddfc9d18abcafb9d3b
Gerrit-Change-Number: 45477
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz
Gerrit-Reviewer: Andrey Petrov andrey.petrov@gmail.com
Gerrit-Reviewer: David Guckian david.guckian@intel.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Vanessa Eusebio vanessa.f.eusebio@intel.com
Gerrit-MessageType: newchange



    