[S] Change in coreboot[master]: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform

[Arthur Heymans (Code Review)]

Attention is currently required from: Patrick Rudolph, Johnny Lin, Christian Walter, Shuming Chu (Shuming).

Arthur Heymans has uploaded a new patch set (#4) to the change originally created by Shuming Chu (Shuming). ( https://review.coreboot.org/c/coreboot/+/71085 )

Change subject: soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform
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soc/intel/xeon_sp: Improve FSP-S boottime for xeon-sp platform

Set up a postcar MTRR solution that caches the full DRAM including TSEG.
FSP-S uses memory above cbmem_top and below TSEG base. Caching that
region dramatically improves boottimes.

TESTED on Archer City 2S: Boottime goes from ~19m to ~4m.

Change-Id: Ib886eda81566b491325e8cd65c9dfb44c89977c7
Signed-off-by: Arthur Heymans 
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M src/soc/intel/xeon_sp/memmap.c
1 file changed, 24 insertions(+), 18 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/71085/4