Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42226 )
Change subject: mb/google/zork: Enable psp_verstage ......................................................................
mb/google/zork: Enable psp_verstage
Finally enable psp_verstage for zork.
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: If6a12c2074d7c84c0cb766393c66f5eff29a58d5 --- M src/mainboard/google/zork/Kconfig A src/mainboard/google/zork/memlayout.ld 2 files changed, 35 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42226/1
diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 9a2e373..aca5640 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -88,8 +88,6 @@ config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH - select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE
config VBOOT_VBNV_OFFSET hex @@ -122,6 +120,21 @@ depends on USE_OEM_BIN default ""
+#TODO: Change these to get the postition from the FMAP file +config PICASSO_FW_A_POSITION + hex + default 0xFF031040 + depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + help + Location of the AMD firmware in the RW_A region. + +config PICASSO_FW_B_POSITION + hex + default 0xFF3CF040 + depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + help + Location of the AMD firmware in the RW_B region + config VARIANT_HAS_FW_CONFIG bool help @@ -134,4 +147,21 @@ help Which board version did FW_CONFIG become valid in CBI.
+config VBOOT_STARTS_BEFORE_BOOTBLOCK + bool "PSP verstage" + depends on HAVE_PRE_BOOTBLOCK_VBOOT_SUPPORT + default y if VBOOT + help + Firmware verification happens before the main processor is brought + online. + +config VBOOT_STARTS_IN_BOOTBLOCK + bool "X86 verstage (in bootblock)" + depends on VBOOT && ! VBOOT_STARTS_BEFORE_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + help + Firmware verification happens during the end of or right after the + bootblock. This implies that a static VBOOT2_WORK() buffer must be + allocated in memlayout. + endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/mainboard/google/zork/memlayout.ld b/src/mainboard/google/zork/memlayout.ld new file mode 100644 index 0000000..5493e0d --- /dev/null +++ b/src/mainboard/google/zork/memlayout.ld @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/memlayout.ld>
Hello build bot (Jenkins), Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42226
to look at the new patch set (#2).
Change subject: mb/google/zork: Enable psp_verstage ......................................................................
mb/google/zork: Enable psp_verstage
Finally enable psp_verstage for zork.
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: If6a12c2074d7c84c0cb766393c66f5eff29a58d5 --- M src/mainboard/google/zork/Kconfig 1 file changed, 32 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42226/2
Eric Peers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42226 )
Change subject: mb/google/zork: Enable psp_verstage ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42226/3/src/mainboard/google/zork/K... File src/mainboard/google/zork/Kconfig:
https://review.coreboot.org/c/coreboot/+/42226/3/src/mainboard/google/zork/K... PS3, Line 125: #TODO: Change these to get the postition from the FMAP file bug #?
https://review.coreboot.org/c/coreboot/+/42226/3/src/mainboard/google/zork/K... PS3, Line 159: # TODO: Remove after testing is complete bug # to remove or date that it should be removed by?
Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Julius Werner, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42226
to look at the new patch set (#4).
Change subject: mb/google/zork: Enable psp_verstage ......................................................................
mb/google/zork: Enable psp_verstage
Finally enable psp_verstage for zork.
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: If6a12c2074d7c84c0cb766393c66f5eff29a58d5 --- M src/mainboard/google/zork/Kconfig 1 file changed, 30 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42226/4
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42226 )
Change subject: mb/google/zork: Enable psp_verstage ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42226/3/src/mainboard/google/zork/K... File src/mainboard/google/zork/Kconfig:
https://review.coreboot.org/c/coreboot/+/42226/3/src/mainboard/google/zork/K... PS3, Line 125: #TODO: Change these to get the postition from the FMAP file
bug #?
Removed - The todo wasn't needed, it's tracked in the bug but the code stands as it is.
https://review.coreboot.org/c/coreboot/+/42226/3/src/mainboard/google/zork/K... PS3, Line 159: # TODO: Remove after testing is complete
bug # to remove or date that it should be removed by?
Removed todo.
Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Julius Werner, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42226
to look at the new patch set (#5).
Change subject: mb/google/zork: Enable psp_verstage ......................................................................
mb/google/zork: Enable psp_verstage
Finally enable psp_verstage for zork.
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: If6a12c2074d7c84c0cb766393c66f5eff29a58d5 --- M src/mainboard/google/zork/Kconfig 1 file changed, 30 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42226/5
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42226 )
Change subject: mb/google/zork: Enable psp_verstage ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42226/5/src/mainboard/google/zork/K... File src/mainboard/google/zork/Kconfig:
https://review.coreboot.org/c/coreboot/+/42226/5/src/mainboard/google/zork/K... PS5, Line 154: default y if VBOOT Do we want to make this default or select it in our chromium configs?
https://review.coreboot.org/c/coreboot/+/42226/5/src/mainboard/google/zork/K... PS5, Line 162: select VBOOT_SEPARATE_VERSTAGE shouldn't we be selecting this for VBOOT_STARTS_BEFORE_BOOTBLOCK as well?
Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Julius Werner, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42226
to look at the new patch set (#6).
Change subject: mb/google/zork: Enable psp_verstage ......................................................................
mb/google/zork: Enable psp_verstage
Finally enable psp_verstage for zork.
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: If6a12c2074d7c84c0cb766393c66f5eff29a58d5 --- M src/mainboard/google/zork/Kconfig 1 file changed, 30 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42226/6
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42226 )
Change subject: mb/google/zork: Enable psp_verstage ......................................................................
Patch Set 6: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/42226/6/src/mainboard/google/zork/K... File src/mainboard/google/zork/Kconfig:
https://review.coreboot.org/c/coreboot/+/42226/6/src/mainboard/google/zork/K... PS6, Line 128: 0xFF031040 Can you provide the command you used to calculate these so they can be double checked? Also if someone wants to update the values at a later date.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42226 )
Change subject: mb/google/zork: Enable psp_verstage ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42226/6/src/mainboard/google/zork/K... File src/mainboard/google/zork/Kconfig:
https://review.coreboot.org/c/coreboot/+/42226/6/src/mainboard/google/zork/K... PS6, Line 128: 0xFF031040
Can you provide the command you used to calculate these so they can be double checked? Also if someo […]
Sure. This is the start of the region in the fmap table with 0x40 added for the cbfs header.
I'm working on getting rid of these and will be updating verstage to find them with cbfs. That needs to happen in the next couple of weeks.
Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Julius Werner, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42226
to look at the new patch set (#7).
Change subject: mb/google/zork: Enable psp_verstage ......................................................................
mb/google/zork: Enable psp_verstage
Finally enable psp_verstage for zork.
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: If6a12c2074d7c84c0cb766393c66f5eff29a58d5 --- M src/mainboard/google/zork/Kconfig 1 file changed, 32 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42226/7
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42226 )
Change subject: mb/google/zork: Enable psp_verstage ......................................................................
Patch Set 7: Code-Review+2
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42226 )
Change subject: mb/google/zork: Enable psp_verstage ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42226/5/src/mainboard/google/zork/K... File src/mainboard/google/zork/Kconfig:
https://review.coreboot.org/c/coreboot/+/42226/5/src/mainboard/google/zork/K... PS5, Line 154: default y if VBOOT
Do we want to make this default or select it in our chromium configs?
I think we want to make it the default. I was thinking we'd remove the bootblock option for zork relatively soon.
https://review.coreboot.org/c/coreboot/+/42226/5/src/mainboard/google/zork/K... PS5, Line 162: select VBOOT_SEPARATE_VERSTAGE
shouldn't we be selecting this for VBOOT_STARTS_BEFORE_BOOTBLOCK as well?
It automatically gets selected by selecting VBOOT_STARTS_BEFORE_BOOTBLOCK, so there's no need to do it here.
Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42226 )
Change subject: mb/google/zork: Enable psp_verstage ......................................................................
mb/google/zork: Enable psp_verstage
Finally enable psp_verstage for zork.
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: If6a12c2074d7c84c0cb766393c66f5eff29a58d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42226 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Raul Rangel rrangel@chromium.org --- M src/mainboard/google/zork/Kconfig 1 file changed, 32 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved
diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 19225d7..a6c866d 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -100,8 +100,6 @@ config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH - select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE
config VBOOT_VBNV_OFFSET hex @@ -123,6 +121,22 @@ hex default 0x50
+config PICASSO_FW_A_POSITION + hex + default 0xFF031040 + depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + help + Location of the AMD firmware in the RW_A region. This is the + start of the RW-A region + 64 bytes for the cbfs header. + +config PICASSO_FW_B_POSITION + hex + default 0xFF3CF040 + depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + help + Location of the AMD firmware in the RW_B region. This is the + start of the RW-A region + 64 bytes for the cbfs header. + config VARIANT_HAS_FW_CONFIG bool help @@ -151,4 +165,20 @@ default 2 if BOARD_GOOGLE_VILBOZ default VARIANT_MIN_BOARD_ID_V3_SCHEMATICS
+config VBOOT_STARTS_BEFORE_BOOTBLOCK + bool "PSP verstage" + default y if VBOOT + help + Firmware verification happens before the main processor is brought + online. + +config VBOOT_STARTS_IN_BOOTBLOCK + bool "X86 verstage (in bootblock)" + depends on VBOOT && ! VBOOT_STARTS_BEFORE_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + help + Firmware verification happens during the end of or right after the + bootblock. This implies that a static VBOOT2_WORK() buffer must be + allocated in memlayout. + endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ
Raul Rangel has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/42226 )
Change subject: mb/google/zork: Enable psp_verstage ......................................................................
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42226 )
Change subject: mb/google/zork: Enable psp_verstage ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42226/10/src/mainboard/google/zork/... File src/mainboard/google/zork/Kconfig:
https://review.coreboot.org/c/coreboot/+/42226/10/src/mainboard/google/zork/... PS10, Line 171: help Why is this a visible option? Does not build if selected and VBOOT=n.
https://review.coreboot.org/c/coreboot/+/42226/10/src/mainboard/google/zork/... PS10, Line 178: select VBOOT_SEPARATE_VERSTAGE This asymmetry is confusing to me, it's a VBOOT_SEPARATE_VERSTAGE=y in the VBOOT_STARTS_BEFORE_BOOTBLOCK case too.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42226 )
Change subject: mb/google/zork: Enable psp_verstage ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42226/10/src/mainboard/google/zork/... File src/mainboard/google/zork/Kconfig:
https://review.coreboot.org/c/coreboot/+/42226/10/src/mainboard/google/zork/... PS10, Line 138: RW-A RW-B?