Change in coreboot[master]: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg

[Werner Zeh (Code Review)]

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63777 )

Change subject: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg
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Patch Set 1: Code-Review+1

(1 comment)

File src/soc/intel/common/block/fast_spi/fast_spi_def.h:

https://review.coreboot.org/c/coreboot/+/63777/comment/95f55c2d_93ee0e1d 
PS1, Line 78: #define SPIBAR_HSFSTS_W1C_BITS		(0xff | SPIBAR_HSFSTS_SAF_CE)
Maybe better

#define SPIBAR_HSFSTS_W1C_BITS		(SPIBAR_HSFSTS_SAF_CE | 0xff)

To honor the bit location in the register?