Attention is currently required from: Angel Pons.
Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69031 )
Change subject: nb/intel: Include <cpu/cpu.h> instead of <arch/cpu.h> ......................................................................
nb/intel: Include <cpu/cpu.h> instead of <arch/cpu.h>
Also sort includes.
Change-Id: I2cfea04513f3ca4478038d29742d6ca48695d68e Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/haswell/report_platform.c M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/sandybridge/early_dmi.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/x4x/raminit.c 7 files changed, 60 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/69031/1
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 4196edf..46040af 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1,18 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <commonlib/helpers.h> -#include <stdint.h> -#include <arch/cpu.h> -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <device/pci_def.h> -#include <device/device.h> -#include <device/smbus_host.h> -#include <spd.h> #include <console/console.h> -#include <lib.h> +#include <cpu/cpu.h> #include <delay.h> +#include <device/device.h> +#include <device/mmio.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/smbus_host.h> +#include <lib.h> +#include <spd.h> +#include <stdint.h> #include <timestamp.h> + #include "gm45.h" #include "chip.h"
diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 0b5319b..778108e 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -1,12 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h> -#include <arch/cpu.h> +#include <cpu/cpu.h> #include <cpu/intel/microcode.h> -#include <string.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <device/pci_ops.h> #include <cpu/x86/msr.h> +#include <device/pci_ops.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <string.h> + #include "haswell.h"
static void report_cpu_info(void) diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index b765417..dc576d6 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -1,15 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <stdint.h> -#include <console/console.h> #include <arch/io.h> -#include <device/pci_ops.h> -#include <device/pci_def.h> -#include <elog.h> -#include <cpu/x86/msr.h> +#include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> -#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <elog.h> +#include <stdint.h>
#include "ironlake.h"
diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index d9b7ed2..b01bbbd 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <arch/cpu.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/model_206ax/model_206ax.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 5044512..3042daa 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -1,19 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <console/console.h> -#include <commonlib/region.h> +#include <cbmem.h> #include <cf9_reset.h> -#include <string.h> -#include <arch/cpu.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <device/smbus_host.h> -#include <cbmem.h> -#include <timestamp.h> #include <mrc_cache.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <cpu/x86/msr.h> +#include <string.h> +#include <timestamp.h> #include <types.h>
#include "raminit_native.h" diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index a308d07..d30ac25 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -1,33 +1,34 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/hpet.h> +#include <cbfs.h> +#include <cbmem.h> +#include <cf9_reset.h> #include <console/console.h> #include <console/usb.h> -#include <cf9_reset.h> -#include <string.h> +#include <cpu/cpu.h> #include <device/device.h> #include <device/dram/ddr3.h> -#include <device/pci_ops.h> -#include <arch/cpu.h> -#include <cbmem.h> -#include <cbfs.h> -#include <ip_checksum.h> -#include <pc80/mc146818rtc.h> #include <device/pci_def.h> +#include <device/pci_ops.h> +#include <ip_checksum.h> #include <lib.h> +#include <memory_info.h> #include <mrc_cache.h> -#include <spd.h> +#include <pc80/mc146818rtc.h> +#include <security/vboot/vboot_common.h> #include <smbios.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <spd.h> #include <stddef.h> #include <stdint.h> +#include <string.h> #include <timestamp.h> + #include "raminit.h" #include "pei_data.h" #include "sandybridge.h" #include "chip.h" -#include <security/vboot/vboot_common.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <memory_info.h>
/* Management Engine is in the southbridge */ #include <southbridge/intel/bd82x6x/me.h> diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index b4366fb..4efbb56 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -1,16 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <device/pci_ops.h> -#include <device/smbus_host.h> #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> -#include <arch/cpu.h> -#include <spd.h> -#include <string.h> +#include <cpu/cpu.h> #include <device/dram/ddr2.h> #include <device/dram/ddr3.h> +#include <device/pci_ops.h> +#include <device/smbus_host.h> #include <mrc_cache.h> +#include <spd.h> +#include <string.h> #include <timestamp.h> #include <types.h>