Change in coreboot[master]: nb/intel/gm45: Put register definitions into separate files

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45450 )

Change subject: nb/intel/gm45: Put register definitions into separate files
......................................................................

nb/intel/gm45: Put register definitions into separate files

MCHBAR registers are scattered throughout raminit, and located next to
the code using them. Therefore, they have not been moved in this patch.

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: I9bb3c907565ef2a278b748b1b7771dbd11d42df9
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/gm45/gm45.h
A src/northbridge/intel/gm45/registers/dmibar.h
A src/northbridge/intel/gm45/registers/epbar.h
A src/northbridge/intel/gm45/registers/host_bridge.h
4 files changed, 93 insertions(+), 68 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/45450/1

diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 4c16abf..061bf2d 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -184,27 +184,8 @@
 /*
  * D0:F0
  */
-#define D0F0_EPBAR_LO		0x40
-#define D0F0_EPBAR_HI		0x44
-#define D0F0_MCHBAR_LO		0x48
-#define D0F0_MCHBAR_HI		0x4c
-#define D0F0_GGC		0x52
-#define D0F0_DEVEN		0x54
-#define D0F0_PCIEXBAR_LO	0x60
-#define D0F0_PCIEXBAR_HI	0x64
-#define D0F0_DMIBAR_LO		0x68
-#define D0F0_DMIBAR_HI		0x6c
-#define D0F0_PMBASE		0x78
-#define D0F0_PAM(x)		(0x90 + (x)) /* 0-6 */
-#define D0F0_REMAPBASE		0x98
-#define D0F0_REMAPLIMIT		0x9a
-#define D0F0_SMRAM		0x9d
-#define D0F0_ESMRAMC		0x9e
-#define D0F0_TOM		0xa0
-#define D0F0_TOUUD		0xa2
-#define D0F0_TOLUD		0xb0
-#define D0F0_SKPD		0xdc /* Scratchpad Data */
-#define D0F0_CAPID0		0xe0
+
+#include "registers/host_bridge.h"

/*
  * D1:F0 PEG
@@ -361,29 +342,7 @@
 #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x)))
 #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x)))

-#define DMIVCECH	0x000	/* 32bit */
-#define DMIPVCCAP1	0x004	/* 32bit */
-
-#define DMIVC0RCAP	0x010	/* 32bit */
-#define DMIVC0RCTL	0x014	/* 32bit */
-#define DMIVC0RSTS	0x01a	/* 16bit */
-#define  VC0NP		(1 << 1)
-
-#define DMIVC1RCAP	0x01c	/* 32bit */
-#define DMIVC1RCTL	0x020	/* 32bit */
-#define DMIVC1RSTS	0x026	/* 16bit */
-#define  VC1NP		(1 << 1)
-
-#define DMIESD		0x044	/* 32bit */
-
-#define DMILE1D		0x050	/* 32bit */
-#define DMILE1A		0x058	/* 64bit */
-#define DMILE2D		0x060	/* 32bit */
-#define DMILE2A		0x068	/* 64bit */
-
-#define DMILCAP		0x084	/* 32bit */
-#define DMILCTL		0x088	/* 16bit */
-#define DMILSTS		0x08a	/* 16bit */
+#include "registers/dmibar.h"

/*
  * EPBAR
@@ -393,30 +352,7 @@
 #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x)))
 #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x)))

-#define EPPVCCAP1	0x004	/* 32bit */
-#define EPPVCCTL	0x00c	/* 32bit */
-
-#define EPVC0RCAP	0x010	/* 32bit */
-#define EPVC0RCTL	0x014	/* 32bit */
-#define EPVC0RSTS	0x01a	/* 16bit */
-
-#define EPVC1RCAP	0x01c	/* 32bit */
-#define EPVC1RCTL	0x020	/* 32bit */
-#define EPVC1RSTS	0x026	/* 16bit */
-
-#define EPVC1MTS	0x028	/* 32bit */
-#define EPVC1ITC	0x02c	/* 32bit */
-
-#define EPVC1IST	0x038	/* 64bit */
-
-#define EPESD		0x044	/* 32bit */
-
-#define EPLE1D		0x050	/* 32bit */
-#define EPLE1A		0x058	/* 64bit */
-#define EPLE2D		0x060	/* 32bit */
-#define EPLE2A		0x068	/* 64bit */
-
-#define EP_PORTARB(x)	(0x100 + 4 * (x))	/* 256bit */
+#include "registers/epbar.h"

#ifndef __ACPI__

diff --git a/src/northbridge/intel/gm45/registers/dmibar.h b/src/northbridge/intel/gm45/registers/dmibar.h
new file mode 100644
index 0000000..2ece871
--- /dev/null
+++ b/src/northbridge/intel/gm45/registers/dmibar.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __GM45_REGISTERS_DMIBAR_H__
+#define __GM45_REGISTERS_DMIBAR_H__
+
+#define DMIVCECH	0x000	/* 32bit */
+#define DMIPVCCAP1	0x004	/* 32bit */
+
+#define DMIVC0RCAP	0x010	/* 32bit */
+#define DMIVC0RCTL	0x014	/* 32bit */
+#define DMIVC0RSTS	0x01a	/* 16bit */
+#define  VC0NP		(1 << 1)
+
+#define DMIVC1RCAP	0x01c	/* 32bit */
+#define DMIVC1RCTL	0x020	/* 32bit */
+#define DMIVC1RSTS	0x026	/* 16bit */
+#define  VC1NP		(1 << 1)
+
+#define DMIESD		0x044	/* 32bit */
+
+#define DMILE1D		0x050	/* 32bit */
+#define DMILE1A		0x058	/* 64bit */
+#define DMILE2D		0x060	/* 32bit */
+#define DMILE2A		0x068	/* 64bit */
+
+#define DMILCAP		0x084	/* 32bit */
+#define DMILCTL		0x088	/* 16bit */
+#define DMILSTS		0x08a	/* 16bit */
+
+#endif /* __GM45_REGISTERS_DMIBAR_H__ */
diff --git a/src/northbridge/intel/gm45/registers/epbar.h b/src/northbridge/intel/gm45/registers/epbar.h
new file mode 100644
index 0000000..6342844
--- /dev/null
+++ b/src/northbridge/intel/gm45/registers/epbar.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __GM45_REGISTERS_EPBAR_H__
+#define __GM45_REGISTERS_EPBAR_H__
+
+#define EPPVCCAP1	0x004	/* 32bit */
+#define EPPVCCTL	0x00c	/* 32bit */
+
+#define EPVC0RCAP	0x010	/* 32bit */
+#define EPVC0RCTL	0x014	/* 32bit */
+#define EPVC0RSTS	0x01a	/* 16bit */
+
+#define EPVC1RCAP	0x01c	/* 32bit */
+#define EPVC1RCTL	0x020	/* 32bit */
+#define EPVC1RSTS	0x026	/* 16bit */
+
+#define EPVC1MTS	0x028	/* 32bit */
+#define EPVC1ITC	0x02c	/* 32bit */
+
+#define EPVC1IST	0x038	/* 64bit */
+
+#define EPESD		0x044	/* 32bit */
+
+#define EPLE1D		0x050	/* 32bit */
+#define EPLE1A		0x058	/* 64bit */
+#define EPLE2D		0x060	/* 32bit */
+#define EPLE2A		0x068	/* 64bit */
+
+#define EP_PORTARB(x)	(0x100 + 4 * (x))	/* 256bit */
+
+#endif /* __GM45_REGISTERS_EPBAR_H__ */
diff --git a/src/northbridge/intel/gm45/registers/host_bridge.h b/src/northbridge/intel/gm45/registers/host_bridge.h
new file mode 100644
index 0000000..4d50d39
--- /dev/null
+++ b/src/northbridge/intel/gm45/registers/host_bridge.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __GM45_REGISTERS_HOST_BRIDGE_H__
+#define __GM45_REGISTERS_HOST_BRIDGE_H__
+
+#define D0F0_EPBAR_LO		0x40
+#define D0F0_EPBAR_HI		0x44
+#define D0F0_MCHBAR_LO		0x48
+#define D0F0_MCHBAR_HI		0x4c
+#define D0F0_GGC		0x52
+#define D0F0_DEVEN		0x54
+#define D0F0_PCIEXBAR_LO	0x60
+#define D0F0_PCIEXBAR_HI	0x64
+#define D0F0_DMIBAR_LO		0x68
+#define D0F0_DMIBAR_HI		0x6c
+#define D0F0_PMBASE		0x78
+#define D0F0_PAM(x)		(0x90 + (x)) /* 0-6 */
+#define D0F0_REMAPBASE		0x98
+#define D0F0_REMAPLIMIT		0x9a
+#define D0F0_SMRAM		0x9d
+#define D0F0_ESMRAMC		0x9e
+#define D0F0_TOM		0xa0
+#define D0F0_TOUUD		0xa2
+#define D0F0_TOLUD		0xb0
+#define D0F0_SKPD		0xdc /* Scratchpad Data */
+#define D0F0_CAPID0		0xe0
+
+#endif /* __GM45_REGISTERS_HOST_BRIDGE_H__ */

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45450 )

Change subject: nb/intel/gm45: Put register definitions into separate files
......................................................................

Patch Set 3:

What's the motivation here?

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45450 )

Change subject: nb/intel/gm45: Put register definitions into separate files
......................................................................

Patch Set 3:
> Patch Set 3:
>
> What's the motivation here?

Basically, to slim down gm45.h (or any other northbridge's <northbridge>.h header). This isn't much of a problem with gm45, though, as there aren't many definitions to move.

[Angel Pons (Code Review)]

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45450 )

Change subject: nb/intel/gm45: Put register definitions into separate files
......................................................................

Abandoned