Change in coreboot[master]: mb/intel/tglrvp: Add support for USB Type-C connector device properties
John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43893 )
Change subject: mb/intel/tglrvp: Add support for USB Type-C connector device properties ......................................................................
mb/intel/tglrvp: Add support for USB Type-C connector device properties
This change updates TGLRVP configuration to have USB Type-C connector device properties filled into ACPI SSDT.
TEST=Built and booted to kernel on tglrvp boards. Verified the USBC scope under LPCB.EC0.CREC with required connector device properties.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Ifd4c59afb3b8a222598fd4ff36d72c4b877bdad2 --- M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/tglrvp/Makefile.inc M src/mainboard/intel/tglrvp/mainboard.c M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 5 files changed, 15 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/43893/1
diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 867c88e..1a05441 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -17,6 +17,7 @@ select INTEL_LPSS_UART_FOR_CONSOLE select DRIVERS_INTEL_ISH select EC_ACPI + select EC_GOOGLE_CHROMEEC_LPC select PCIEXP_HOTPLUG
config CHROMEOS diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc index 065bd4c..cba1909 100644 --- a/src/mainboard/intel/tglrvp/Makefile.inc +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -14,6 +14,7 @@ smm-y += smihandler.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c ramstage-y += mainboard.c ramstage-y += board_id.c
diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c index 7708b85..82877ed 100644 --- a/src/mainboard/intel/tglrvp/mainboard.c +++ b/src/mainboard/intel/tglrvp/mainboard.c @@ -3,6 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <device/device.h> +#include <ec/ec.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <smbios.h> @@ -24,6 +25,8 @@
pads = variant_gpio_table(&num); gpio_configure_pads(pads, num); + + mainboard_ec_init(); }
static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b4a121a..e8dc7bd 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -256,7 +256,11 @@ device pci 1e.1 off end # UART1 0xA0A9 device pci 1e.2 off end # GSPI0 0xA0AA device pci 1e.3 off end # GSPI1 0xA0AB - device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # eSPI 0xA080 - A09F device pci 1f.1 on end # P2SB 0xA0A0 device pci 1f.2 hidden # PMC 0xA0A1 # The pmc_mux chip driver is a placeholder for the diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index b08cd3c..14f454f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -252,7 +252,11 @@ device pci 1e.1 off end # UART1 0xA0A9 device pci 1e.2 off end # GSPI0 0xA0AA device pci 1e.3 off end # GSPI1 0xA0AB - device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # eSPI 0xA080 - A09F device pci 1f.1 on end # P2SB 0xA0A0 device pci 1f.2 hidden end # PMC 0xA0A1 device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Wonkyu Kim, Caveh Jalali, Tim Wawrzynczak, Duncan Laurie, Shamile Khan, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43893
to look at the new patch set (#2).
Change subject: mb/intel/tglrvp: Add support for USB Type-C connector device properties ......................................................................
mb/intel/tglrvp: Add support for USB Type-C connector device properties
This change updates TGLRVP configuration to have USB Type-C connector device properties filled into ACPI SSDT.
TEST=Built and booted to kernel on tglrvp boards. Verified the USBC scope under LPCB.EC0.CREC with required connector device properties.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Ifd4c59afb3b8a222598fd4ff36d72c4b877bdad2 --- M src/mainboard/intel/tglrvp/Makefile.inc A src/mainboard/intel/tglrvp/ec.c M src/mainboard/intel/tglrvp/mainboard.c M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 5 files changed, 72 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/43893/2
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Wonkyu Kim, Caveh Jalali, Tim Wawrzynczak, Duncan Laurie, Shamile Khan, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43893
to look at the new patch set (#3).
Change subject: mb/intel/tglrvp: Add support for USB Type-C connector device properties ......................................................................
mb/intel/tglrvp: Add support for USB Type-C connector device properties
This change updates TGLRVP configuration to have USB Type-C connector device properties filled into ACPI SSDT.
TEST=Built and booted to kernel on tglrvp boards. Verified the USBC scope under LPCB.EC0.CREC with required connector device properties.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Ifd4c59afb3b8a222598fd4ff36d72c4b877bdad2 --- M src/mainboard/intel/tglrvp/Makefile.inc A src/mainboard/intel/tglrvp/ec.c M src/mainboard/intel/tglrvp/mainboard.c M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 6 files changed, 74 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/43893/3
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43893 )
Change subject: mb/intel/tglrvp: Add support for USB Type-C connector device properties ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43893/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/ec.c:
https://review.coreboot.org/c/coreboot/+/43893/3/src/mainboard/intel/tglrvp/... PS3, Line 11: static void ramstage_ec_init(void) : { : const struct google_chromeec_event_info info = { : .log_events = MAINBOARD_EC_LOG_EVENTS, : .sci_events = MAINBOARD_EC_SCI_EVENTS, : .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, : .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, : .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, : }; : : printk(BIOS_DEBUG, "mainboard: EC init\n"); : : google_chromeec_events_init(&info, acpi_is_wakeup_s3()); : } This should be all that you need to include in `mainboard_ec_init()`, the ec_lpc module will initialize the LPC decoding (as done below)
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Wonkyu Kim, Shreesh Chhabbi, Caveh Jalali, Tim Wawrzynczak, Duncan Laurie, Shamile Khan, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43893
to look at the new patch set (#4).
Change subject: mb/intel/tglrvp: Add support for USB Type-C connector device properties ......................................................................
mb/intel/tglrvp: Add support for USB Type-C connector device properties
This change updates TGLRVP configuration to have USB Type-C connector device properties filled into ACPI SSDT.
TEST=Built and booted to kernel on tglrvp boards. Verified the USBC scope under LPCB.EC0.CREC with required connector device properties.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Ifd4c59afb3b8a222598fd4ff36d72c4b877bdad2 --- M src/mainboard/intel/tglrvp/Makefile.inc A src/mainboard/intel/tglrvp/ec.c M src/mainboard/intel/tglrvp/mainboard.c M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 6 files changed, 35 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/43893/4
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43893 )
Change subject: mb/intel/tglrvp: Add support for USB Type-C connector device properties ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43893/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/ec.c:
https://review.coreboot.org/c/coreboot/+/43893/3/src/mainboard/intel/tglrvp/... PS3, Line 11: static void ramstage_ec_init(void) : { : const struct google_chromeec_event_info info = { : .log_events = MAINBOARD_EC_LOG_EVENTS, : .sci_events = MAINBOARD_EC_SCI_EVENTS, : .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, : .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, : .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, : }; : : printk(BIOS_DEBUG, "mainboard: EC init\n"); : : google_chromeec_events_init(&info, acpi_is_wakeup_s3()); : }
This should be all that you need to include in `mainboard_ec_init()`, the ec_lpc module will initial […]
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43893 )
Change subject: mb/intel/tglrvp: Add support for USB Type-C connector device properties ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43893 )
Change subject: mb/intel/tglrvp: Add support for USB Type-C connector device properties ......................................................................
mb/intel/tglrvp: Add support for USB Type-C connector device properties
This change updates TGLRVP configuration to have USB Type-C connector device properties filled into ACPI SSDT.
TEST=Built and booted to kernel on tglrvp boards. Verified the USBC scope under LPCB.EC0.CREC with required connector device properties.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Ifd4c59afb3b8a222598fd4ff36d72c4b877bdad2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43893 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/intel/tglrvp/Makefile.inc A src/mainboard/intel/tglrvp/ec.c M src/mainboard/intel/tglrvp/mainboard.c M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 6 files changed, 35 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc index 065bd4c..cba1909 100644 --- a/src/mainboard/intel/tglrvp/Makefile.inc +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -14,6 +14,7 @@ smm-y += smihandler.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c ramstage-y += mainboard.c ramstage-y += board_id.c
diff --git a/src/mainboard/intel/tglrvp/ec.c b/src/mainboard/intel/tglrvp/ec.c new file mode 100644 index 0000000..14760017 --- /dev/null +++ b/src/mainboard/intel/tglrvp/ec.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <baseboard/ec.h> + +void mainboard_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c index 7708b85..82877ed 100644 --- a/src/mainboard/intel/tglrvp/mainboard.c +++ b/src/mainboard/intel/tglrvp/mainboard.c @@ -3,6 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <device/device.h> +#include <ec/ec.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <smbios.h> @@ -24,6 +25,8 @@
pads = variant_gpio_table(&num); gpio_configure_pads(pads, num); + + mainboard_ec_init(); }
static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h index 52db2af..c018299 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h @@ -41,6 +41,8 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + /* Log EC wake events plus EC shutdown events */ #define MAINBOARD_EC_LOG_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b4a121a..e8dc7bd 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -256,7 +256,11 @@ device pci 1e.1 off end # UART1 0xA0A9 device pci 1e.2 off end # GSPI0 0xA0AA device pci 1e.3 off end # GSPI1 0xA0AB - device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # eSPI 0xA080 - A09F device pci 1f.1 on end # P2SB 0xA0A0 device pci 1f.2 hidden # PMC 0xA0A1 # The pmc_mux chip driver is a placeholder for the diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 097ae68..ef8de3c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -252,7 +252,11 @@ device pci 1e.1 off end # UART1 0xA0A9 device pci 1e.2 off end # GSPI0 0xA0AA device pci 1e.3 off end # GSPI1 0xA0AB - device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # eSPI 0xA080 - A09F device pci 1f.1 on end # P2SB 0xA0A0 device pci 1f.2 hidden # PMC 0xA0A1 # The pmc_mux chip driver is a placeholder for the
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John Zhao (Code Review) -
Patrick Georgi (Code Review)
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Tim Wawrzynczak (Code Review)