Attention is currently required from: Hung-Te Lin, Kiwi Liu, Paul Menzel, Yidi Lin, Yu-Ping Wu.
Mengqi Zhang has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email )
Change subject: soc/mediatek/common: Correct src clk frq to 400 MHz for eMMMC clk of 400 kHz ......................................................................
Patch Set 15:
(8 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84298/comment/a8dae5a1_b8a70943?usp... : PS14, Line 7: Reduce eMMC clock frequency to 400kHz
Correct src clk frq to 400 MHz for eMMMC clk of 400 kHz
Done
https://review.coreboot.org/c/coreboot/+/84298/comment/3c879739_a73e0962?usp... : PS14, Line 10: power-on.
power-on due to wrong src_hz value.
Done
https://review.coreboot.org/c/coreboot/+/84298/comment/0710f6bd_b1779c00?usp... : PS14, Line 11: When we need to set a clock output frequency, we actually set a
leave one blank line above.
Done
https://review.coreboot.org/c/coreboot/+/84298/comment/e42662eb_716ec1c8?usp... : PS14, Line 13: he frequency : division value to 125
I don't think the origin code will give us the 125 value due to the division rounding error. […]
Done
https://review.coreboot.org/c/coreboot/+/84298/comment/fedb8840_5aeba80a?usp... : PS14, Line 16: 400KHz.
move to next line.
Done
https://review.coreboot.org/c/coreboot/+/84298/comment/8fc23682_e03b777f?usp... : PS14, Line 16: So we correct source clock frequency to 400MHz for eMMC output clock of 400KHz.
leave one blank line above.
Done
File src/soc/mediatek/common/msdc.c:
https://review.coreboot.org/c/coreboot/+/84298/comment/cd82c77b_9717deb6?usp... : PS9, Line 432: host->src_hz = 400 * 1000 * 1000;
According to depthcharge, MT8173's source clock is 200MHz. […]
Done
File src/soc/mediatek/common/msdc.c:
https://review.coreboot.org/c/coreboot/+/84298/comment/9d332d9f_b6ffce93?usp... : PS12, Line 353: msdc_debug("sclk: %d\n", sclk);
before patch: […]
Done