[coreboot-gerrit] Change in ...coreboot[master]: Use uintptr_t instead of (void *) where it makes sense

[Arthur Heymans (Code Review)]

Hello Patrick Rudolph, Julius Werner, build bot (Jenkins), Philipp Hug, ron minnich, Vanessa Eusebio, Huang Jin, York Yang, Lee Leahy, Jonathan Neuschäfer, Philipp Deppenwiese, Nico Huber, Damien Zammit, David Guckian, 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/c/coreboot/+/30684

to look at the new patch set (#12).

Change subject: Use uintptr_t instead of (void *) where it makes sense
......................................................................

Use uintptr_t instead of (void *) where it makes sense

This reduces the number of casts.

Change-Id: I8ef5d9fad0298c79806fd94ca053027822022ac2
Signed-off-by: Arthur Heymans <[e-mail]>
---
M src/arch/x86/acpi_bert_storage.c
M src/arch/x86/cbmem.c
M src/arch/x86/include/arch/bert_storage.h
M src/cpu/allwinner/a10/cbmem.c
M src/cpu/allwinner/a10/ram_segs.h
M src/cpu/amd/family_10h-family_15h/ram_calc.c
M src/cpu/intel/haswell/romstage.c
M src/cpu/intel/haswell/stage_cache.c
M src/cpu/intel/model_206ax/stage_cache.c
M src/cpu/ti/am335x/cbmem.c
M src/drivers/amd/agesa/mtrr_fixme.c
M src/drivers/intel/fsp1_0/fsp_util.c
M src/drivers/intel/fsp1_1/include/fsp/memmap.h
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/drivers/intel/fsp1_1/stack.c
M src/drivers/intel/fsp1_1/stage_cache.c
M src/drivers/intel/fsp2_0/hob_verify.c
M src/drivers/intel/fsp2_0/include/fsp/memmap.h
M src/drivers/intel/fsp2_0/stage_cache.c
M src/include/cbmem.h
M src/include/imd.h
M src/include/stage_cache.h
M src/lib/ext_stage_cache.c
M src/lib/imd.c
M src/mainboard/emulation/qemu-armv7/cbmem.c
M src/mainboard/emulation/qemu-i440fx/memory.c
M src/mainboard/emulation/qemu-power8/cbmem.c
M src/northbridge/intel/e7505/memmap.c
M src/northbridge/intel/fsp_rangeley/raminit.c
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/gm45/ram_calc.c
M src/northbridge/intel/haswell/ram_calc.c
M src/northbridge/intel/i440bx/ram_calc.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/i945/ram_calc.c
M src/northbridge/intel/nehalem/ram_calc.c
M src/northbridge/intel/pineview/northbridge.c
M src/northbridge/intel/pineview/ram_calc.c
M src/northbridge/intel/sandybridge/ram_calc.c
M src/northbridge/intel/x4x/northbridge.c
M src/northbridge/intel/x4x/ram_calc.c
M src/northbridge/via/vx900/memmap.c
M src/soc/amd/stoneyridge/cpu.c
M src/soc/amd/stoneyridge/include/soc/northbridge.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/ramtop.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/cavium/cn81xx/cbmem.c
M src/soc/imgtec/pistachio/cbmem.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/memmap.c
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/baytrail/memmap.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/baytrail/stage_cache.c
M src/soc/intel/braswell/cpu.c
M src/soc/intel/braswell/memmap.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/broadwell/memmap.c
M src/soc/intel/broadwell/romstage/romstage.c
M src/soc/intel/broadwell/stage_cache.c
D src/soc/intel/cannonlake/cbmem.c
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/romstage/romstage.c
M src/soc/intel/cannonlake/smmrelocate.c
M src/soc/intel/common/block/include/intelblocks/smm.h
M src/soc/intel/common/block/smm/smm.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/denverton_ns/cpu.c
M src/soc/intel/denverton_ns/include/soc/smm.h
M src/soc/intel/denverton_ns/memmap.c
M src/soc/intel/denverton_ns/romstage.c
M src/soc/intel/fsp_baytrail/memmap.c
M src/soc/intel/fsp_baytrail/northcluster.c
M src/soc/intel/fsp_broadwell_de/memmap.c
D src/soc/intel/icelake/cbmem.c
M src/soc/intel/icelake/memmap.c
M src/soc/intel/icelake/romstage/romstage.c
M src/soc/intel/icelake/smmrelocate.c
M src/soc/intel/quark/memmap.c
M src/soc/intel/quark/northcluster.c
M src/soc/intel/quark/romstage/fsp2_0.c
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
M src/soc/intel/skylake/smmrelocate.c
M src/soc/mediatek/common/cbmem.c
M src/soc/nvidia/tegra124/cbmem.c
M src/soc/nvidia/tegra210/cbmem.c
M src/soc/qualcomm/ipq40xx/cbmem.c
M src/soc/qualcomm/ipq806x/cbmem.c
M src/soc/qualcomm/sdm845/cbmem.c
M src/soc/rockchip/common/cbmem.c
M src/soc/samsung/exynos5250/cbmem.c
M src/soc/samsung/exynos5420/cbmem.c
M src/soc/sifive/fu540/cbmem.c
M src/soc/ucb/riscv/cbmem.c
97 files changed, 259 insertions(+), 334 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/30684/12
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/30684
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8ef5d9fad0298c79806fd94ca053027822022ac2
Gerrit-Change-Number: 30684
Gerrit-PatchSet: 12
Gerrit-Owner: Arthur Heymans <[e-mail]>
Gerrit-Reviewer: Arthur Heymans <[e-mail]>
Gerrit-Reviewer: Damien Zammit <[e-mail]>
Gerrit-Reviewer: David Guckian <[e-mail]>
Gerrit-Reviewer: Huang Jin <[e-mail]>
Gerrit-Reviewer: Jonathan Neuschäfer <[e-mail]>
Gerrit-Reviewer: Julius Werner <[e-mail]>
Gerrit-Reviewer: Lee Leahy <[e-mail]>
Gerrit-Reviewer: Nico Huber <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
Gerrit-Reviewer: Philipp Deppenwiese <[e-mail]>
Gerrit-Reviewer: Philipp Hug <[e-mail]>
Gerrit-Reviewer: Vanessa Eusebio <[e-mail]>
Gerrit-Reviewer: York Yang <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-Reviewer: ron minnich <[e-mail]>
Gerrit-MessageType: newpatchset