Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35030 )
Change subject: soc/intel/skylake: Add Lewisburg family PCH support ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35030/10/src/include/device/pci_ids... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/35030/10/src/include/device/pci_ids... PS10, Line 3244: #define PCI_DEVICE_ID_INTEL_LWB_P2SB 0xa1a0 : #define PCI_DEVICE_ID_INTEL_LWB_P2SB_SUPER 0xa220
Should I add this ID to https://github. […]
I think that's needed.
https://review.coreboot.org/c/coreboot/+/35030/10/src/soc/intel/common/block... File src/soc/intel/common/block/sata/sata.c:
https://review.coreboot.org/c/coreboot/+/35030/10/src/soc/intel/common/block... PS10, Line 81: PCI_DEVICE_ID_INTEL_LWB_SSATA_AHCI_SUPER,
Should I add PCI_DEVICE_ID_INTEL_LWB_(S)SATA_RAID_* here?
I think that's necessary, the driver will need to have those programming even in raid mode.