Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44063 )
Change subject: vc/amd/fsp/picasso: document DXIO lane number mapping ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44063/2/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/44063/2/src/vendorcode/amd/fsp/pica... PS2, Line 141: * GPP[3:2] | [5:4] | PCIe
It would be great to add the pci bridge device and funciton to this because we empirically have a mi […]
I'll have a look; that'll be a follow-up patch though. The assignment of the PCIe engines to lanes isn't fixed, but has some constraints that have to be met.
Looked for some more documentation on Pollock yesterday, but didn't find that much new info.