Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43103 )
Change subject: haswell: Drop GPIO indirection layers ......................................................................
haswell: Drop GPIO indirection layers
This simplifies things and makes type checking possible.
Change-Id: Iefc9baabae286aac2f2c46853adf1f6edf01586f Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43103 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tristan Corrick tristan@corrick.kiwi --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/slippy/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/lenovo/t440p/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/romstage.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/pch.h 11 files changed, 6 insertions(+), 17 deletions(-)
Approvals: build bot (Jenkins): Verified Tristan Corrick: Looks good to me, approved
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index c29e219..a72418a 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -72,7 +72,6 @@
struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, };
romstage_common(&romstage_params); diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 078e87c..73c38e7 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -72,7 +72,6 @@
struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, };
romstage_common(&romstage_params); diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index c49d94f..5d9c37c 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -11,8 +11,6 @@ #include <superio/ite/it8772f/it8772f.h> #include "onboard.h"
-extern const struct pch_lp_gpio_map mainboard_gpio_map[]; - void mainboard_config_rcba(void) { /* @@ -107,7 +105,6 @@
struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, };
/* Early SuperIO setup */ diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index bc14ee0..5261ddc 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -8,8 +8,6 @@ #include <southbridge/intel/lynxpoint/lp_gpio.h> #include "variant.h"
-extern const struct pch_lp_gpio_map mainboard_gpio_map[]; - void mainboard_config_rcba(void) { /* @@ -77,7 +75,6 @@
struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, };
variant_romstage_entry(&romstage_params); diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 58c684d..abbd852 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -114,7 +114,6 @@
struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .copy_spd = NULL, };
diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index 70fc202..bd1020d 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -74,7 +74,6 @@
struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, };
romstage_common(&romstage_params); diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 05725ff..8bcabd9 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -70,7 +70,6 @@
struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, };
romstage_common(&romstage_params); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 1ec4cd1..fa32eca 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -192,7 +192,6 @@ struct pei_data; struct romstage_params { struct pei_data *pei_data; - const void *gpio_map; void (*copy_spd)(struct pei_data *peid); }; void romstage_common(const struct romstage_params *params); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index c3d9a10..8cf2e7c 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -19,7 +19,7 @@
enable_lapic();
- wake_from_s3 = early_pch_init(params->gpio_map); + wake_from_s3 = early_pch_init();
/* Perform some early chipset initialization required * before RAM initialization can work diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 4d29564..92cbf01 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -13,6 +13,7 @@
#if CONFIG(INTEL_LYNXPOINT_LP) #include "lp_gpio.h" +extern const struct pch_lp_gpio_map mainboard_gpio_map[]; #else #include <southbridge/intel/common/gpio.h> #endif @@ -77,16 +78,16 @@ { }
-int early_pch_init(const void *gpio_map) +int early_pch_init(void) { int wake_from_s3;
pch_enable_bars();
#if CONFIG(INTEL_LYNXPOINT_LP) - setup_pch_lp_gpios(gpio_map); + setup_pch_lp_gpios(mainboard_gpio_map); #else - setup_pch_gpios(gpio_map); + setup_pch_gpios(&mainboard_gpio_map); #endif pch_generic_setup();
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 7987486..c59878e 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -121,7 +121,7 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
void enable_usb_bar(void); -int early_pch_init(const void *gpio_map); +int early_pch_init(void); void pch_enable_lpc(void); void mainboard_config_superio(void); void mainboard_config_rcba(void);