[coreboot-gerrit] Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue

[Angel Pons (Code Review)]

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Meera Ravindranath.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 )

Change subject: mb/adlrvp: Fix DDR5 Boot issue
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Patch Set 8:

(1 comment)

File src/mainboard/intel/adlrvp/romstage_fsp_params.c:

https://review.coreboot.org/c/coreboot/+/50996/comment/d3937633_0b35098a 
PS8, Line 63: 			mupd->FspmConfig.SpdAddressTable[i] = spd_array[i];
I imagine this patch is a quick and dirty workaround to fix a boot issue so that others can test things. Still, I'd appreciate if you could refine this.