[coreboot-gerrit] Change in coreboot[master]: mb/google/hatch: Enable/disable GPIO clock gating

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34180 )

Change subject: mb/google/hatch: Enable/disable GPIO clock gating
......................................................................

mb/google/hatch: Enable/disable GPIO clock gating

Before the system enters S0ix or S3, each GPIO community
will have its dynamic clock gating turned on.  Upon return
to S0, the dynamic clock gating will be turned back off.

BUG=b:130764684
BRANCH=none
TEST=Used dut-power to verify that the clock gating is enabled
in S0ix and S3.  Also used Store(..., Debug) statements in the
ASL code to verify it was getting called.

Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf
Signed-off-by: Tim Wawrzynczak 
---
M src/mainboard/google/hatch/dsdt.asl
A src/mainboard/google/hatch/mainboard.asl
2 files changed, 90 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/34180/1

diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl
index 87e98ea..e2959a7 100644
--- a/src/mainboard/google/hatch/dsdt.asl
+++ b/src/mainboard/google/hatch/dsdt.asl
@@ -41,6 +41,9 @@
    		#include <soc/intel/cannonlake/acpi/northbridge.asl>
    		#include <soc/intel/cannonlake/acpi/southbridge.asl>
    	}
+
+		/* Mainboard hooks */
+		#include "mainboard.asl"
    }

#if CONFIG(CHROMEOS)
diff --git a/src/mainboard/google/hatch/mainboard.asl b/src/mainboard/google/hatch/mainboard.asl
new file mode 100644
index 0000000..a8f5dc1
--- /dev/null
+++ b/src/mainboard/google/hatch/mainboard.asl
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/gpio.h>
+
+/*
+ * ConfiGure Power Management
+ * for GPIO communities
+ *
+ * Arg0: GPIO community (0-4)
+ * Arg1: 0=PM off, 1=PM on
+ */
+Method (CGPM, 2, Serialized)
+{
+	/*
+	 * _SB.PCI0.GCFG = Get GPIO MISCCFG Register Address
+	 */
+	OperationRegion (PREG, SystemMemory, _SB.PCI0.GCFG (Arg0), 4)
+	Field (PREG, ByteAcc, NoLock, Preserve)
+	{
+		REG, 32
+	}
+
+	If (LEqual (Arg1, 0)) {
+		/* Read register, mask off PM bits, write back */
+		Store (REG, Local1)
+		Store (LAnd (Local1, LNot (MISCCFG_ENABLE_GPIO_PM_CONFIG)), Local1)
+		Store (Local1, REG)
+	} Else {
+		/* Read register, OR in the PM bits, write back */
+		Store (REG, Local1)
+		Store (LOr (Local1, MISCCFG_ENABLE_GPIO_PM_CONFIG), Local1)
+		Store (Local1, REG)
+	}
+}
+
+/*
+ * Method called from _PTS prior to sleep state entry
+ * Enables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MPTS, 1, Serialized)
+{
+	For (Local0 = 0, Local0 < 5, Local0++)
+	{
+		CGPM (Local0, 1)
+	}
+}
+
+/*
+ * Method called from _WAK prior to system sleep state wakeup
+ * Disables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MWAK, 1, Serialized)
+{
+	For (Local0 = 0, Local0 < 5, Local0++)
+	{
+		CGPM (Local0, 0)
+	}
+}
+
+/* Called from _SB.LPID._DSM */
+Method (MS0X, 1, Serialized)
+{
+	If (Arg0 == 1) {
+		For (Local0 = 0, Local0 < 5, Local0++)
+		{
+			CGPM (Local0, 1)
+		}
+	} Else {
+		For (Local0 = 0, Local0 < 5, Local0++)
+		{
+			CGPM (Local0, 0)
+		}
+	}
+}