Hello build bot (Jenkins), Wonkyu Kim, Caveh Jalali, Shamile Khan, Prashant Malani, Divya Sasidharan, Nick Vaccaro, Brandon Breitenstein, Patrick Rudolph, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42056
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMs ......................................................................
soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMs
The Connect Topology Command(CNTP) is sent with default timeout value (0x1388) along with FW CM. The CNTP is supposed to be skipped while using SW CM. While transition from FW CM to SW CM, the default timeout value could cause boot time delay up to ~10 seconds. Set this FSPS UPD ITbtConnectTopologyTimeoutInMs to be 0 in order to avoid the 10 seconds delay. Future FSP release will evaluate this ITbtConnectTopologyTimeoutInMs value. While FSP finds this UPD value being 0, FSP will skip sending CNTP.
BUG=b:155893566 TEST=Built image with SW CM Thunderbolt firmware and verified no outstanding delay time while using FSP v3197 during boot to kernel.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I47e3519fd818cb56e6abd16464d8370ffddabc5b --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/42056/3