Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46260
to look at the new patch set (#14).
Change subject: soc/intel/common: Add PCIe Runtime D3 driver for ACPI ......................................................................
soc/intel/common: Add PCIe Runtime D3 driver for ACPI
This driver is for devices attached to a PCIe root port that support Runtime D3. It creates the necessary PowerResource in the root port to provide _ON/_OFF methods for which will turn off power and clocks to the device when it is in the D3cold state.
The mainboard declares the driver in devicetree and provides the GPIOs that control power/reset for the device attached to the root port and the SRCCLK pin used for the PMC IPC mailbox to enable/disable the clock.
An additional device property is created for storage devices if it matches the PCI storage class which is used to indicate that the storage device should use D3 for power savings.
BUG=b:160996445 TEST=boot on volteer device with this driver enabled in the devicetree and disassemble the SSDT to ensure this code exists.
Signed-off-by: Duncan Laurie dlaurie@google.com Change-Id: I13e59c996b4f5e4c2657694bda9fad869b64ffde --- M src/soc/intel/common/block/pcie/Kconfig M src/soc/intel/common/block/pcie/Makefile.inc A src/soc/intel/common/block/pcie/rtd3/Kconfig A src/soc/intel/common/block/pcie/rtd3/Makefile.inc A src/soc/intel/common/block/pcie/rtd3/chip.h A src/soc/intel/common/block/pcie/rtd3/rtd3.c 6 files changed, 362 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/46260/14