Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... File src/soc/intel/alderlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... PS2, Line 177: GPD nit: line up with the others
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 235: : /* Group E */ : #define GPP_E0_IRQ 0x26 : #define GPP_E1_IRQ 0x27 : #define GPP_E2_IRQ 0x28 : #define GPP_E3_IRQ 0x29 : #define GPP_E4_IRQ 0x30 : #define GPP_E5_IRQ 0x31 : #define GPP_E6_IRQ 0x32 : #define GPP_E7_IRQ 0x33 : #define GPP_E8_IRQ 0x34 : #define GPP_E9_IRQ 0x35 : #define GPP_E10_IRQ 0x36 : #define GPP_E11_IRQ 0x37 : #define GPP_E12_IRQ 0x38 : #define GPP_E13_IRQ 0x39 : #define GPP_E14_IRQ 0x3A : #define GPP_E15_IRQ 0x3B : #define GPP_E16_IRQ 0x3C : #define GPP_E17_IRQ 0x3D : #define GPP_E18_IRQ 0x3E : #define GPP_E19_IRQ 0x3F : #define GPP_E20_IRQ 0x40 : #define GPP_E21_IRQ 0x41 : #define GPP_E22_IRQ 0x42 : #define GPP_E23_IRQ 0x43 can you move this between D and F?
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 23: 27 I don't see more than 24