[coreboot-gerrit] Change in coreboot[master]: google/link: fix detection of dimm on channel 1

[Matt DeVillier (Code Review)]

Hello Patrick Rudolph, Angel Pons, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35084

to look at the new patch set (#2).

Change subject: google/link: fix detection of dimm on channel 1
......................................................................

google/link: fix detection of dimm on channel 1

Changes to the sandybridge memory init code (both MRC
and native) now require SPD data on all populated channels
in order for dimms to be detected properly, so copy
spd_data[0] to spd_data[2], as LINK always has 2
channels of memory down.

Test: boot google/link, observe onboard RAM correctly
detected on both channels

Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe
Signed-off-by: Matt DeVillier 
---
M src/mainboard/google/link/romstage.c
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/35084/2