Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34132 )
Change subject: soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timer ......................................................................
soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timer
This patch moves USE_LEGACY_8254_TIMER Kconfig into common/block/timer for better code sharing. Also ported CB:33512 for SPT and ICP PCH.
Change-Id: Ic767ff97aaa3eb7fa35ffa38fa416d006eaa6e78 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34132 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/timer/Kconfig M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/espi.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/lpc.c 9 files changed, 20 insertions(+), 35 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index fed7f02..4235b7a 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -316,14 +316,6 @@ Setting non-zero value will allow to use DBC or DCI to debug SOC. PlatformDebugConsent in FspmUpd.h has the details.
-config USE_LEGACY_8254_TIMER - bool "Use Legacy 8254 Timer" - default y if PAYLOAD_SEABIOS - default n - help - This sets the Enable8254ClockGating UPD, which according to the FSP Integration - guide needs to be disabled in order to boot SeaBIOS, but should otherwise be enabled. - config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xe00 diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig index a415045..a214ef0 100644 --- a/src/soc/intel/common/block/timer/Kconfig +++ b/src/soc/intel/common/block/timer/Kconfig @@ -2,3 +2,13 @@ bool help Intel Processor common TIMER support + +config USE_LEGACY_8254_TIMER + bool "Use Legacy 8254 Timer" + default y if PAYLOAD_SEABIOS || VGA_ROM_RUN + default n + help + This sets the FSP UPD to enable Legacy 8254 clock gating. As per + the FSP Integration guide Legacy 8254 timer clock gating UPD needs + to be disabled in order to boot SeaBIOS or run OpRom, + but should otherwise be enabled. diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 028f6b2..72596c4 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -204,8 +204,6 @@ /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable;
- /* Statically clock gate 8254 PIT. */ - uint8_t clock_gate_8254; /* Enable C6 DRAM */ uint8_t enable_c6dram; /* diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index a4b6d80..a98821c 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -199,16 +199,6 @@ outb((1 << 7), 0x70); };
-static void clock_gate_8254(const struct device *dev) -{ - const config_t *config = dev->chip_info; - - if (!config->clock_gate_8254) - return; - - itss_clock_gate_8254(); -} - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ @@ -229,7 +219,6 @@ soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); - clock_gate_8254(dev); soc_mirror_dmi_pcr_io_dec(); }
diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 8b65a89..03b00d9 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -124,6 +124,10 @@ /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
+ /* Legacy 8254 timer support */ + params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGatingOnS3 = 1; + /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable;
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 7f28340..7fbe9e5 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -237,6 +237,9 @@ params->SlowSlewRateForSa = config->SlowSlewRateForSa; params->FastPkgCRampDisable = config->FastPkgCRampDisable;
+ /* Legacy 8254 timer support */ + params->Early8254ClockGatingEnable = !CONFIG_USE_LEGACY_8254_TIMER; + soc_irq_settings(params); }
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 9c8e2bf..da941dc 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -513,9 +513,6 @@ /* Enable/Disable host reads to PMC XRAM registers */ u8 PchPmPmcReadDisable;
- /* Statically clock gate 8254 PIT. */ - u8 clock_gate_8254; - /* * Use SD card detect GPIO with default config: * - Edge triggered diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 08f5d79..a1fced2 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -315,6 +315,9 @@ /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
+ /* Legacy 8254 timer support */ + params->Early8254ClockGatingEnable = !CONFIG_USE_LEGACY_8254_TIMER; + memcpy(params->SerialIoDevMode, config->SerialIoDevMode, sizeof(params->SerialIoDevMode));
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 8d6228c..d8e5ccc 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -96,16 +96,6 @@ REG_SCRIPT_END };
-static void clock_gate_8254(struct device *dev) -{ - const config_t *config = dev->chip_info; - - if (!config->clock_gate_8254) - return; - - itss_clock_gate_8254(); -} - void lpc_soc_init(struct device *dev) { const config_t *const config = dev->chip_info; @@ -125,5 +115,4 @@ soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); - clock_gate_8254(dev); }