Attention is currently required from: Patrick Rudolph. HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50327 )
Change subject: sb/intel/bd82x6x/acpi: Convert to ASL 2.0 ......................................................................
sb/intel/bd82x6x/acpi: Convert to ASL 2.0
Change-Id: Ib587d7a982852e7123e43337407ef20d96811719 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/acpi/usb.asl 2 files changed, 53 insertions(+), 53 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/50327/1
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index e873f55..b9b718f 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -108,53 +108,53 @@ /* Set flag to enable USB charging in S3 */ Method (S3UE) { - Store (One, \S3U0) - Store (One, \S3U1) + \S3U0 = 1 + \S3U1 = 1 }
/* Set flag to disable USB charging in S3 */ Method (S3UD) { - Store (Zero, \S3U0) - Store (Zero, \S3U1) + \S3U0 = 0 + \S3U1 = 0 }
/* Set flag to enable USB charging in S5 */ Method (S5UE) { - Store (One, \S5U0) - Store (One, \S5U1) + \S5U0 = 1 + \S5U1 = 1 }
/* Set flag to disable USB charging in S5 */ Method (S5UD) { - Store (Zero, \S5U0) - Store (Zero, \S5U1) + \S5U0 = 0 + \S5U1 = 0 }
/* Set flag to enable 3G module in S3 */ Method (S3GE) { - Store (One, \S33G) + \S33G = 1 }
/* Set flag to disable 3G module in S3 */ Method (S3GD) { - Store (Zero, \S33G) + \S33G = 0 }
/* Set XHCI Mode enable */ Method (XHCE) { - Store (One, \XHCI) + \XHCI = 1 }
/* Set XHCI Mode disable */ Method (XHCD) { - Store (Zero, \XHCI) + \XHCI = 0 } External (_TZ.SKIN)
@@ -176,46 +176,46 @@ /* Update Fan 0 thresholds */ Method (F0UT, 2) { - Store (Arg0, \F0OF) - Store (Arg1, \F0ON) + \F0OF = Arg0 + \F0ON = Arg1 TZUP () }
/* Update Fan 1 thresholds */ Method (F1UT, 2) { - Store (Arg0, \F1OF) - Store (Arg1, \F1ON) + \F1OF = Arg0 + \F1ON = Arg1 TZUP () }
/* Update Fan 2 thresholds */ Method (F2UT, 2) { - Store (Arg0, \F2OF) - Store (Arg1, \F2ON) + \F2OF = Arg0 + \F2ON = Arg1 TZUP () }
/* Update Fan 3 thresholds */ Method (F3UT, 2) { - Store (Arg0, \F3OF) - Store (Arg1, \F3ON) + \F3OF = Arg0 + \F3ON = Arg1 TZUP () }
/* Update Fan 4 thresholds */ Method (F4UT, 2) { - Store (Arg0, \F4OF) - Store (Arg1, \F4ON) + \F4OF = Arg0 + \F4ON = Arg1 TZUP () }
/* Update Temperature Sensor ID */ Method (TMPU, 1) { - Store (Arg0, \TMPS) + \TMPS = Arg0 TZUP () } diff --git a/src/southbridge/intel/bd82x6x/acpi/usb.asl b/src/southbridge/intel/bd82x6x/acpi/usb.asl index 309053f..15a2f9b 100644 --- a/src/southbridge/intel/bd82x6x/acpi/usb.asl +++ b/src/southbridge/intel/bd82x6x/acpi/usb.asl @@ -37,12 +37,12 @@ })
// REV: Revision 0x02 for ACPI 5.0 - CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) - Store (0x02, REV) + CreateField (DerefOf (PCKG [0]), 0, 0x07, REV) + REV = 0x02
// VISI: Port visibility to user per port - CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) - Store (Arg0, VISI) + CreateField (DerefOf (PCKG [0]), 0x40, 1, VISI) + VISI = Arg0
Return (PCKG) } @@ -90,12 +90,12 @@ })
// REV: Revision 0x02 for ACPI 5.0 - CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) - Store (0x02, REV) + CreateField (DerefOf (PCKG [0]), 0, 0x07, REV) + REV = 0x02
// VISI: Port visibility to user per port - CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) - Store (Arg0, VISI) + CreateField (DerefOf (PCKG [0]), 0x40, 1, VISI) + VISI = Arg0
Return (PCKG) } @@ -137,38 +137,38 @@ CreateDWordField(Arg1,0,CDW1)
// Check revision - If(LNotEqual(Arg0,One)) { + If(Arg0 != 1) { // Set unknown revision bit - Or(CDW1,0x8,CDW1) + CDW1 |= 8 }
// Set failure if xHCI is disabled by coreboot - If(LEqual(XHCI, 0)) { - Or(CDW1,0x2,CDW1) + If(XHCI == 0) { + CDW1 |= 2 }
// Query flag clear and xHCI in auto mode - If(LAnd(LNot(And(CDW1,0x1)),LOr(LEqual(XHCI ,2), LEqual(XHCI ,3)))) { - Store ("XHCI Switch", Debug) - Store(Zero, Local0) - And(XPRT, 0x3, Local0) - If(LOr(LEqual(Local0, 0), LEqual(Local0, 1))) { - Store(0xF, Local1) + If(!(CDW1 & 0x1) && (XHCI == 2 || XHCI == 3)) { + Debug = "XHCI Switch" + Local0 = 0 + Local0 = XPRT & 0x03 + If(Local0 == 0 || Local0 == 1) { + Local1 = 0x0f } - ElseIf(LEqual(Local0, 2)) { - Store(0x3, Local1) + ElseIf(Local0 == 2) { + Local1 = 3 } - ElseIf(LEqual(Local0, 3)) { - Store(Zero, Local1) + ElseIf(Local0 == 3) { + Local1 = 0 } - And(RPM3, 0xFFFFFFF0, Local0) - Or(Local0, Local1, RPM3) - And(PRM2, 0xFFFFFFF0, Local0) - Or(Local0, Local1, PRM2) - And(SSEN, 0xFFFFFFF0, Local0) - Or(Local0, Local1, SSEN) - And(X2PR, 0xFFFFFFF0, Local0) - Or(Local0, Local1, X2PR) + Local0 = RPM3 & 0xfffffff0 + RPM3 = Local0 | Local1 + Local0 = PRM2 & 0xfffffff0 + PRM2 = Local0 | Local1 + Local0 = SSEN & 0xfffffff0 + SSEN = Local0 | Local1 + Local0 = X2PR & 0xfffffff0 + X2PR = Local0 | Local1 } Return(Arg1) }