Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48279 )
Change subject: soc/intel/common: Move CSE Lite driver functionality into romstage ......................................................................
soc/intel/common: Move CSE Lite driver functionality into romstage
The patch sets up the CSE Lite driver in the romstage instead of ramstage. With this change, CSE Lite driver sets CSE's boot partition and triggers CSE FW update in the romstage. The cse_fw_sync() must be called after DRAM initialization as HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) is expected to be executed after DRAM initialization. With this change, it improves the cold boot time by ~154ms.
Test=Verified on JSL and TGL platforms BUG=b:174694480
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48279 Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 3 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index d2f94a4..30eb78e 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -1,7 +1,7 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c -ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c +romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c
ifeq ($(CONFIG_SOC_INTEL_CSE_RW_UPDATE),y) diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 1d261ea..036a50a 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -775,7 +775,7 @@ return 0; }
-void cse_fw_sync(void *unused) +void cse_fw_sync(void) { static struct get_bp_info_rsp cse_bp_info;
@@ -814,5 +814,3 @@ cse_trigger_recovery(CSE_LITE_SKU_RW_SWITCH_ERROR); } } - -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL); diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 64ee0dd..1a95e2e 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -236,7 +236,7 @@ * In software triggered recovery mode, the function allows CSE to boot from whatever is * currently selected partition. */ -void cse_fw_sync(void *unused); +void cse_fw_sync(void);
/* Perform a board-specific reset sequence for CSE RO<->RW jump */ void cse_board_reset(void);