[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update TCSS PM flow

[Duncan Laurie (Code Review)]

Duncan Laurie has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45014 )

Change subject: soc/intel/tigerlake: Update TCSS PM flow
......................................................................

soc/intel/tigerlake: Update TCSS PM flow

There is requirement to change PM flow for S0ix along with TBT firmware
update under device attached and no device attached scenarios. This
change invokes D3CE and D3CX in DMA _PS3 and _PS0 respectively.

BUG=b:158777291
TEST=Validated s0ix cycles for USB4 device attached and no device
attached test cases along with updated TBT firmware rev35.

Signed-off-by: John Zhao 
Change-Id: Iebc8065fe4c8600960d089577608890ab12a95fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45014
Tested-by: build bot (Jenkins) 
Reviewed-by: Duncan Laurie 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/tigerlake/acpi/tcss_dma.asl
M src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
2 files changed, 29 insertions(+), 23 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Duncan Laurie: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
index da2e8fe..f7c4117 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
@@ -32,20 +32,12 @@

Method (_PR0)
 {
-	If (DUID == 0) {
-		Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 })
-	} Else {
-		Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT1 })
-	}
+	Return (Package() { _SB.PCI0.D3C })
 }

Method (_PR3)
 {
-	If (DUID == 0) {
-		Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 })
-	} Else {
-		Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT1 })
-	}
+	Return (Package() { _SB.PCI0.D3C })
 }

/*
@@ -72,6 +64,24 @@
  */
 Name (SD3C, 0)

+Method (_PS0, 0, Serialized)
+{
+	If (DUID == 0) {
+		_SB.PCI0.TBT0._ON()
+	} Else {
+		_SB.PCI0.TBT1._ON()
+	}
+}
+
+Method (_PS3, 0, Serialized)
+{
+	If (DUID == 0) {
+		_SB.PCI0.TBT0._OFF()
+	} Else {
+		_SB.PCI0.TBT1._OFF()
+	}
+}
+
 Method (_DSW, 3)
 {
    /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */
diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
index abca5d1..b4c0cef 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
@@ -76,10 +76,14 @@

Method (_DSW, 3)
 {
-	C2PM (Arg0, Arg1, Arg2, DCPM)
    /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */
-	_SB.PCI0.TDM0.SD3C = Arg1
-	_SB.PCI0.TDM1.SD3C = Arg1
+	If ((TUID == 0) || (TUID == 1)) {
+		_SB.PCI0.TDM0.SD3C = Arg1
+	} Else {
+		_SB.PCI0.TDM1.SD3C = Arg1
+	}
+
+	C2PM (Arg0, Arg1, Arg2, DCPM)
 }

Method (_PRW, 0)
@@ -302,20 +306,12 @@

Method (_PR0)
 {
-	If ((TUID == 0) || (TUID == 1)) {
-		Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 })
-	} Else {
-		Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT1 })
-	}
+	Return (Package() { _SB.PCI0.D3C })
 }

Method (_PR3)
 {
-	If ((TUID == 0) || (TUID == 1)) {
-		Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 })
-	} Else {
-		Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT1 })
-	}
+	Return (Package() { _SB.PCI0.D3C })
 }

/*