Wim Vervoorn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37704 )
Change subject: soc/intel/skylake: Change SA_PCIEX_LENGTH to 256MB ......................................................................
Patch Set 1:
Patch Set 1:
The number of busses is typically configurable in PCI configuration, which afaik is done by FSP. ACPI has to match the hardware configuration, so the commit message should say if that is the case and how it was tested/verified.
The space used here depends on the assigned bus numbers, no on the enabled root ports.
The coreboot code is in theory free to assign any bus number between 0 and 255 to a bus it configures. There is no dependency on FSP. I also looked and the hardware specification and could not find a way that the bus number assigned can be limited (by masking bits e.g.)
So what I have done is change the values and checked it the area was reserved and reported properly and doesn't overlap. Please note, it is valid to limit the area if a huge amount of MMIO is needed and you are sure no bus above 63 is used. But then you do this on purpose and know where the dmesg reporting comes from.