Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36700 )
Change subject: sb/intel/i82801gx: Add common LPC decode code ......................................................................
Patch Set 5:
(5 comments)
https://review.coreboot.org/c/coreboot/+/36700/2/src/mainboard/getac/p470/de... File src/mainboard/getac/p470/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/36700/2/src/mainboard/getac/p470/de... PS2, Line 66: register "gen1_dec" = "0x00fc0601" : register "gen1_dec"
gen_2 and 3?
Done
https://review.coreboot.org/c/coreboot/+/36700/5/src/mainboard/gigabyte/ga-9... File src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/36700/5/src/mainboard/gigabyte/ga-9... PS5, Line 82: ???
A comment says this is SuperIO Power Management Events. I guess the "???" means that the SIO datasheet doesn't mention such a thing?
No such range is set up. so it's likely something else that vendor sets up.
https://review.coreboot.org/c/coreboot/+/36700/1/src/mainboard/gigabyte/ga-g... File src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/36700/1/src/mainboard/gigabyte/ga-g... PS1, Line 53: gen1_dec"
pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291); ?
Done
https://review.coreboot.org/c/coreboot/+/36700/1/src/mainboard/ibase/mb899/d... File src/mainboard/ibase/mb899/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/36700/1/src/mainboard/ibase/mb899/d... PS1, Line 42: register "gen1_dec" = "0x00fc0291" : register "gen2_dec" = "0x00000301"
pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0291); […]
Done
https://review.coreboot.org/c/coreboot/+/36700/5/src/mainboard/kontron/986lc... File src/mainboard/kontron/986lcd-m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/36700/5/src/mainboard/kontron/986lc... PS5, Line 45: ??
A comment says "io 0x300 decode". I wonder what this would be useful for.
No idea. These configs are often just copied from vendor.