[coreboot-gerrit] Change in coreboot[master]: soc/intel/{cnl, icl}: Cache the TSEG region

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35026 )

Change subject: soc/intel/{cnl, icl}: Cache the TSEG region
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Patch Set 2:
> #2 With POSTCAR_STAGE=y and (CB:34995 + CB: 35026) [romstage -> postcar -> ramstage]
>
> Aug 23
> > Total Time: 818,078
>
> Total Time till picking kernel: 818,078
>  Total Time till picking payload: 639,809

For this commit 36b7091 exactly, I want to see full 'cbmem -t' data as I am trying to figure out the mystery of timestamp 1100, where we seem to consistently loose 10ms if we gained 7ms earlier.