Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32907
Change subject: [WIP] Documentation: How to run coreboot on PC Engines apu1 ......................................................................
[WIP] Documentation: How to run coreboot on PC Engines apu1
There were no documentation about running coreboot on apu1 platform, so now it describes how to do this.
Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4 --- A Documentation/mainboard/pcengines/apu1.md A Documentation/mainboard/pcengines/apu1c1_flash.jpg 2 files changed, 63 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32907/1
diff --git a/Documentation/mainboard/pcengines/apu1.md b/Documentation/mainboard/pcengines/apu1.md new file mode 100644 index 0000000..20259a6 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu1.md @@ -0,0 +1,63 @@ +# PC Engines apu1 + +This page describes how to run coreboot on PC Engines apu1 platform. + +## Technology + +| | | +| -----------|:-------------------------------------------------------| +| CPU | AMD G series T40E APU | +| CPU core | 1 GHz dual core (Bobcat core) with 64 bit support | +| | 32K data + 32K instruction + 512KB L2 cache per core | +| DRAM | 2 or 4 GB DDR3-1066 DRAM | +| Boot | From SD card, USB, m-SATA | +| Power | 6 to 12W of 12V power | +| Firmware | coreboot with support for iPXE and USB boot | + +## Flashing coreboot + +| Type | Value | +|---------------------|:-----------| +| Socketed flash | no | +| Model | MX25L1606E | +| Size | 2 MiB | +| Package | SOP-8 | +| Write protection | no | +| Dual BIOS feature | no | +| Internal flashing | yes | + +### Internal programming + +The SPI flash can be accessed using [flashrom]. It is important to execute +command with a `-c <chipname>` argument: + +`flashrom -p internal -c MX25L1606E -w coreboot.rom ` + +### External programming + +**IMPORTANT**: When programming SPI flash, first you need to enter apu1 in S5 +(Soft-off) power state. More details about that state is available in ACPI +Specification documentation. + +The external access to flash chip is available through standard SOP-8 clip or +SOP-8 header which is next to the flash chip on the board. Notice that not all +boards have a header soldered down originally. Hence, there could be an empty +slot with 8 eyelets, so you can solder down a header on your own. The SPI flash +chip and SPI header are marked in the picture below. + +There is no restrictions as to programmer device. However, [flashrom] is +strongly recommended. The example command to program SPI flash with a linux_spi +is: + +`flashrom -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 -c +"MX25L1606E"` + + +**apu1 platform with marked in SPI header and SPI flash chip** +![][apu1c1_flash] + +[apu1c1_flash]: apu1c1_flash.jpg + + +[flashrom]: https://flashrom.org/Flashrom +[here]: https://www.coreboot.org/Binary_situation diff --git a/Documentation/mainboard/pcengines/apu1c1_flash.jpg b/Documentation/mainboard/pcengines/apu1c1_flash.jpg new file mode 100644 index 0000000..069e976 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu1c1_flash.jpg Binary files differ