Attention is currently required from: Andrey Petrov, Patrick Rudolph. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49899 )
Change subject: soc/intel/*: Update microcode as specified for MP-init ......................................................................
soc/intel/*: Update microcode as specified for MP-init
Remove second microcode update in init_one_cpu() and move it to the right place: * It must happen after SMM has been relocated * It must happen after PRMRR has been set up * It must happen before clearing MCEs
Change-Id: Idf2b009ac9dd7cd462abe0f787f27b09feb6ec5b Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/soc/intel/alderlake/cpu.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 14 files changed, 91 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/49899/1
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 577061c..55cd83c 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -608,6 +608,13 @@ /* All CPUs including BSP will run the following function. */ static void cpu_core_init(struct device *cpu) { + /* + * Update microcode a second time as part of MP-init after SMM has been relocated. + * Must happen before MCEs are cleared, but after PRMRR have been set. + */ + const void *microcode_patch = intel_microcode_find_cached(); + intel_microcode_load_unlocked(microcode_patch); + /* Clear out pending MCEs */ configure_mca();
@@ -681,9 +688,6 @@ { /* Relocate the SMM handler. */ smm_relocate(); - - /* After SMM relocation a 2nd microcode load is required. */ - intel_microcode_load_unlocked(microcode_patch); }
static void post_mp_init(void) diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index e675761..e4373a1 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -88,6 +88,13 @@ { char processor_name[49];
+ /* + * Update microcode a second time as part of MP-init after SMM has been relocated. + * Must happen before MCEs are cleared, but after PRMRR have been set. + */ + const void *microcode_patch = intel_microcode_find_cached(); + intel_microcode_load_unlocked(microcode_patch); + /* Clear out pending MCEs */ configure_mca();
@@ -155,10 +162,6 @@ { /* Relocate the SMM handler. */ smm_relocate(); - - /* After SMM relocation a 2nd microcode load is required. */ - const void *microcode_patch = intel_microcode_find_cached(); - intel_microcode_load_unlocked(microcode_patch); }
static void post_mp_init(void) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 784fc74..79b994cb3 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -424,6 +424,12 @@
static void model_206ax_init(struct device *cpu) { + /* + * Update microcode a second time as part of MP-init after SMM has been relocated. + * Must happen before MCEs are cleared, but after PRMRR have been set. + */ + const void *microcode_patch = intel_microcode_find_cached(); + intel_microcode_load_unlocked(microcode_patch);
/* Clear out pending MCEs */ configure_mca(); @@ -498,10 +504,6 @@ { /* Relocate the SMM handler. */ smm_relocate(); - - /* After SMM relocation a 2nd microcode load is required. */ - const void *microcode_patch = intel_microcode_find_cached(); - intel_microcode_load_unlocked(microcode_patch); }
static void post_mp_init(void) diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 9fab277..d53d9a1 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -64,6 +64,13 @@ /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { + /* + * Update microcode a second time as part of MP-init after SMM has been relocated. + * Must happen before MCEs are cleared, but after PRMRR have been set. + */ + const void *microcode_patch = intel_microcode_find_cached(); + intel_microcode_load_unlocked(microcode_patch); + /* Clear out pending MCEs */ /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 8250be5..27ab216 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -53,6 +53,13 @@ if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) prmrr_core_configure();
+ /* + * Update microcode a second time as part of MP-init after SMM has been relocated. + * Must happen before MCEs are cleared, but after PRMRR have been set. + */ + const void *microcode_patch = intel_microcode_find_cached(); + intel_microcode_load_unlocked(microcode_patch); + /* Clear out pending MCEs */ /* TODO(adurbin): Some of these banks are core vs package scope. For now every CPU clears every bank. */ diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index e624240..c034512a 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -35,6 +35,13 @@ printk(BIOS_DEBUG, "Init BayTrail core.\n");
/* + * Update microcode a second time as part of MP-init after SMM has been relocated. + * Must happen before MCEs are cleared, but after PRMRR have been set. + */ + const void *microcode_patch = intel_microcode_find_cached(); + intel_microcode_load_unlocked(microcode_patch); + + /* * The turbo disable bit is actually scoped at building block level -- not package. * For non-BSP cores that are within a building block, enable turbo. The cores within * the BSP's building block will just see it already enabled and move on. @@ -158,9 +165,6 @@
/* Relocate SMM space. */ smm_initiate_relocation(); - - /* Load microcode after SMM relocation. */ - intel_microcode_load_unlocked(pattrs->microcode_patch); }
static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 0c6f463..f704858 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -34,6 +34,13 @@ { printk(BIOS_DEBUG, "Init Braswell core.\n");
+ /* + * Update microcode a second time as part of MP-init after SMM has been relocated. + * Must happen before MCEs are cleared, but after PRMRR have been set. + */ + const void *microcode_patch = intel_microcode_find_cached(); + intel_microcode_load_unlocked(microcode_patch); + /* Enable the local cpu apics */ setup_lapic();
@@ -167,9 +174,6 @@
/* Relocate SMM space. */ smm_initiate_relocation(); - - /* Load microcode after SMM relocation. */ - intel_microcode_load_unlocked(pattrs->microcode_patch); }
static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index f4b72ab..77a4833 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -93,6 +93,13 @@ /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { + /* + * Update microcode a second time as part of MP-init after SMM has been relocated. + * Must happen before MCEs are cleared, but after PRMRR have been set. + */ + const void *microcode_patch = intel_microcode_find_cached(); + intel_microcode_load_unlocked(microcode_patch); + /* Clear out pending MCEs */ /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 2c90aac..ed5f8d2 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -26,16 +26,8 @@ /* no-op */ }
-static void init_one_cpu(struct device *dev) -{ - soc_core_init(dev); - - const void *microcode_patch = intel_microcode_find_cached(); - intel_microcode_load_unlocked(microcode_patch); -} - static struct device_operations cpu_dev_ops = { - .init = init_one_cpu, + .init = soc_core_init, };
static const struct cpu_device_id cpu_table[] = { diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index d0fa019..c692f64 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -58,6 +58,13 @@ /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { + /* + * Update microcode a second time as part of MP-init after SMM has been relocated. + * Must happen before MCEs are cleared, but after PRMRR have been set. + */ + const void *microcode_patch = intel_microcode_find_cached(); + intel_microcode_load_unlocked(microcode_patch); + /* Clear out pending MCEs */ /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 1734ba6..996eced 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -91,6 +91,13 @@ /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { + /* + * Update microcode a second time as part of MP-init after SMM has been relocated. + * Must happen before MCEs are cleared, but after PRMRR have been set. + */ + const void *microcode_patch = intel_microcode_find_cached(); + intel_microcode_load_unlocked(microcode_patch); + /* Clear out pending MCEs */ /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 6518945..f64e8a7 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -58,6 +58,13 @@ /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { + /* + * Update microcode a second time as part of MP-init after SMM has been relocated. + * Must happen before MCEs are cleared, but after PRMRR have been set. + */ + const void *microcode_patch = intel_microcode_find_cached(); + intel_microcode_load_unlocked(microcode_patch); + /* Clear out pending MCEs */ /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 01be4cb..603e4ef 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -102,6 +102,13 @@ if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) prmrr_core_configure();
+ /* + * Update microcode a second time as part of MP-init after SMM has been relocated. + * Must happen before MCEs are cleared, but after PRMRR have been set. + */ + const void *microcode_patch = intel_microcode_find_cached(); + intel_microcode_load_unlocked(microcode_patch); + /* Clear out pending MCEs */ /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 36dfa1b..3394f8a 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -64,6 +64,13 @@ /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { + /* + * Update microcode a second time as part of MP-init after SMM has been relocated. + * Must happen before MCEs are cleared, but after PRMRR have been set. + */ + const void *microcode_patch = intel_microcode_find_cached(); + intel_microcode_load_unlocked(microcode_patch); + /* Clear out pending MCEs */ /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears