Attention is currently required from: Ravindra N. Hello Ravindra N,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/57757
to review the following change.
Change subject: Alderlake: Enable _CPC nominal performance and _CPC nominal frequency in performance scale ......................................................................
Alderlake: Enable _CPC nominal performance and _CPC nominal frequency in performance scale
Signed-off-by: Ravindra N ravindra@intel.corp-partner.google.com Change-Id: I9f09e93a9be97dfe5404c4551a2080180dd850ac --- M src/acpi/acpigen.c M src/cpu/intel/common/common_init.c M src/soc/intel/alderlake/Kconfig M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c 5 files changed, 87 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/57757/1
diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index c8f1437..8e0da29 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -1780,21 +1780,25 @@ break; case 2: max = CPPC_MAX_FIELDS_VER_2; + acpigen_write_name(CPPC_PACKAGE_NAME); break; case 3: max = CPPC_MAX_FIELDS_VER_3; + acpigen_write_name(CPPC_PACKAGE_NAME); break; default: printk(BIOS_ERR, "ERROR: CPPC version %u is not implemented\n", config->version); return; } - acpigen_write_name(CPPC_PACKAGE_NAME);
/* Adding 2 to account for length and version fields */ acpigen_write_package(max + 2); acpigen_write_dword(max + 2);
+ printk(BIOS_DEBUG, "config->regs[0].addrl= %d, config->regs[0].addrh= %d\n", + config->regs[0].addrl, config->regs[0].addrh); + acpigen_write_byte(config->version);
for (i = 0; i < max; ++i) { @@ -1811,7 +1815,7 @@
void acpigen_write_CPPC_method(void) { - char pscope[16]; + char pscope[18]; snprintf(pscope, sizeof(pscope), CONFIG_ACPI_CPU_STRING "." CPPC_PACKAGE_NAME, 0);
acpigen_write_method("_CPC", 0); diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index c5f43ef..f24aac9 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -265,8 +265,17 @@ if (version >= 3) { /* Lowest Frequency */ config->regs[CPPC_LOWEST_FREQ] = unsupported; + + msr.addrl = MSR_PLATFORM_INFO; + + /* + * Nominal Performance -> Maximum Non-Turbo Ratio: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0xce, 0x04,)}, + */ + msr.bit_offset = 8; + /* Nominal Frequency */ - config->regs[CPPC_NOMINAL_FREQ] = unsupported; + config->regs[CPPC_NOMINAL_FREQ] = msr; }
/* diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 915dd3f..2b8584e 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -48,6 +48,7 @@ select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC + select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC_V3 select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index 07e9bea..f1b547f 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -8,6 +8,9 @@ config SOC_INTEL_COMMON_BLOCK_ACPI_GPIO bool
+config SOC_INTEL_COMMON_BLOCK_ACPI_CPPC_V3 + bool + config SOC_INTEL_COMMON_BLOCK_ACPI_LPIT bool depends on HAVE_ACPI_TABLES diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 164631d..7d0d725 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -23,6 +23,26 @@
#define CPUID_6_EAX_ISST (1 << 7)
+/* Performance scaling factor for big core and small core */ +#define ScalingFactorBigCore 100 +#define ScalingFactorSmallCore 79 + +/* Function returns the core type + * 0 - small core + * 1 - big core +*/ +bool get_coretype(int core_id); + +/* Function returns the nominal frequency */ +int get_nominal_frequency(void); + +/* Hybrid cores i.e small core and big core + * function gets the required nominal frequency and based on the + * core type performance scaling factor calculated and performance + * for each core calculated and configures the msr registers +*/ +void hybrid_cpu_cppc_config(struct cppc_config *config, int core_id); + __attribute__((weak)) unsigned long acpi_fill_mcfg(unsigned long current) { /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ @@ -374,19 +394,54 @@ acpigen_write_TSS_package(entries, soc_tss_table); }
-static void generate_cppc_entries(int core_id) +bool get_coretype(int core_id) { + if(core_id == 0 || core_id == 1) { + return 1; //Big Core + } else { + return 0; //Small Core + } +} + +int get_nominal_frequency() +{ + return (cpu_get_max_ratio() * cpu_get_bus_clock()); +} + +void hybrid_cpu_cppc_config(struct cppc_config *config, int core_id) +{ + bool type = get_coretype(core_id); + int nominal_frequency = get_nominal_frequency(); + config->regs[22].addrl = (u16) nominal_frequency; + + if(!type) { + config->regs[3].addrh = (u16) ((nominal_frequency * ScalingFactorSmallCore) / 100); + } else { + config->regs[3].addrh = (u16) ((nominal_frequency * ScalingFactorBigCore) / 100); + } + + printk(BIOS_DEBUG, "hybrid_core type=%d, nominal_frequency=%d, config->regs[3].addrh=%d, config->regs[3].addrl=%d, ((nominal_frequency * ScalingFactorSmallCore) / 100) = %d, config->regs[0].addrl=%d\n", type, nominal_frequency, config->regs[3].addrh, config->regs[3].addrl, ((nominal_frequency * ScalingFactorSmallCore) / 100), config->regs[0].addrl); +} + +static void generate_cppc_entries(int core_id, int version) +{ + struct cppc_config cppc_config; + if (!(CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPPC) && cpuid_eax(6) & CPUID_6_EAX_ISST)) return;
/* Generate GCPC package in first logical core */ if (core_id == 0) { - struct cppc_config cppc_config; - cpu_init_cppc_config(&cppc_config, CPPC_VERSION_2); - acpigen_write_CPPC_package(&cppc_config); + if(version <= 2) { + cpu_init_cppc_config(&cppc_config, CPPC_VERSION_2); + } else { + cpu_init_cppc_config(&cppc_config, CPPC_VERSION_3); + } + acpigen_write_CPPC_package(&cppc_config); } - + + hybrid_cpu_cppc_config(&cppc_config, core_id); /* Write _CPC entry for each logical core */ acpigen_write_CPPC_method(); } @@ -401,6 +456,7 @@ int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; int plen = 6; int totalcores = dev_count_cpu(); + int version = 2; unsigned int num_virt; unsigned int num_phys;
@@ -411,6 +467,9 @@ printk(BIOS_DEBUG, "Found %d CPU(s) with %d/%d physical/logical core(s) each.\n", numcpus, num_phys, num_virt);
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPPC_V3)) { + version = 3; + } for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { for (core_id = 0; core_id < num_virt; core_id++) { if (core_id > 0) { @@ -425,7 +484,7 @@ /* Generate C-state tables */ generate_c_state_entries();
- generate_cppc_entries(core_id); + generate_cppc_entries(core_id, version);
/* Soc specific power states generation */ soc_power_states_generation(core_id, num_virt); @@ -440,3 +499,5 @@ /* Add a method to notify processor nodes */ acpigen_write_processor_cnot(num_virt); } + +