[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Modify FSP-T code caching parameters

[Johnny Lin (Code Review)]

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39625 )

Change subject: soc/intel/xeon_sp: Modify FSP-T code caching parameters
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Patch Set 2:

(1 comment)
> Patch Set 1:
>
> (1 comment)

https://review.coreboot.org/c/coreboot/+/39625/1/src/soc/intel/xeon_sp/bootb... 
File src/soc/intel/xeon_sp/bootblock/bootblock.c:

https://review.coreboot.org/c/coreboot/+/39625/1/src/soc/intel/xeon_sp/bootb... 
PS1, Line 33: 		.CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE),
            : 		.CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE,
> The value we need here has nothing to do with CBFS. […]

With the same FSP after setting them to 0, it can boot to OS but sometimes it takes 7 minutes to boot, this depends on how FSP is implemented but 7 minutes is too long.